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Digital Synchronous On-chip Programmable System

Posted on:2008-03-18Degree:MasterType:Thesis
Country:ChinaCandidate:L HuangFull Text:PDF
GTID:2208360242456525Subject:Signal and Information Processing
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Deferred precise creation and control technique of electrical pulse or light pulse in a lot ofexperiment research is having time resolution and testing applying broadly. The multi-path laserpulse practicing shooting not only need consistent wave form and power, but also need has veryhigh time compatibility, to reach power balance within the field in the inertial confinement fusion,because multi-path target practice laser pulse demands to have triggering strictly in-phase, triggersignal swaying less than 10 ps(≤10ps) in the time domain, less than 10 ps(≤10ps) of deferredprecision and easily programmed.Designing a precise synchronous system is suggested for thispurpose.The thesis erects a problem, which uses with the inertial confinement fusion to the needconcentrating the time synchronism technology with digital circuit, and realizes on the FPGAboard with programmable technology. The digital synchronism realization method has the valuestudying content mainly, and has the certain application.The thesis's main part works is making use of the high density and high-performancecharacteristics of FPGA chips, we are researching for the way of integration synchronismtechnology is arrived at simplifying the system structure within monolithic FPGA chip (includethe interface logic and control logical for the RS232 protocol), which is named SOPC(System Ona programmable chip).the result of this design style transform can higher the flexibility andstability of the whole digital system. System adopts the MFC frame programming to havedesigned that controls procedures of the super ordination machine, we realized serialcommunication of RS232 protocol between the deferred synchronous with the high frequencycounting system and the total control platform,and we analyzed the creation mechanism oftriggering jitters, adopt a timing constraint to restrain the clock generator or transfer circuit, anddesigned synchronous counting of high frequency, counting clock frequency has reached 160 MHz,so we realized 6.25 ns step-by-step adjusting accuracy with four channels of synchronous pulseoutput.Based on these study contents, we carry out the research of developing the digitalsynchronism technology with system on a programmable chip which has embedded core ofprocessors. Because of its standard electronic criterion and interface specification, it isn't difficultto produce a full-function integration synchronism system for the research kingdom of inertialconfinement fusion.
Keywords/Search Tags:in-phase counter, triggering jitter, SOPC(system on a programmable chip), inner-system verify, timing constraint
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