"linear Low Overshoot Voltage Regulator Design And Research

The content of this thesis is to design a low dropout regulator which can be applied to an asynchronous3V or5V smart IC card interface. This LDO can provide stable power supply which has lower overshoot voltage.The theory of LDO is that the negative feedback regulates the output voltage of the circuit. Then the output voltage is insensitive to the power supply and the load current. The thesis discusses the theory of LDO, the optimization and trade-off of the parameters, which provides theoretical basis for circuit designing. Based on this, a new LDO circuit is proposed. The new circuit is composed by the PMOS regulator, the band-gap reference, the over-current protection module, soft-start module, the transient-enhanced module and so on. The performance of LDO circuit is improved with these modules. The innovations of the new circuit are as follows:①According to the control signal, the new circuit applies5V or3V voltages modes to expand the application of the new chip.②The soft-start module makes the output voltage increased linearly to reduce the overshoot voltage.③The transient-enhanced module improves the load transient response.④The output voltage is stable and the ripple is small.⑤The maximal value of output current is80mA in5V mode and65mA in3V mode.⑥The over-current protection module to prevents the output current exceeding the rated current.The function verification and parameter simulation had been done with Hspice software based on CSMC0.5μm Bi-CMOS process. The results of simulation verified the correctness of the theory, and the performances met the requirements of the DATA SHEET. The designing of circuit achieves the expected functions.