Development Of Satellite Payload Data Loader

Payload occupies the central position of the entire satellite system, and thehigh cost and great technical difficulty always make its lead time far behind othersubsystems. It not only affects the test schedule, but also brings great risks to theexpensive satellite onbord equipment for using the real payload in the satellite test.So to develop corresponding test device become inevitable. However, the existingtest device can only simulate the payload data, and cannot build a complete datalink from payload to data transmission system. The structure and fuction of theexisting test decive is too simple to locate and recurrence problems. For these testrequirements, this thesis designed a satellite payload data loader with hierarchicaltest function. The payload data loader can not only simulate the payload dataeffectively, but also simulate the stand-alones of the data transmission systemhierarchically with multiple circuit boards. It meets the requirements well andbrings great flexibility to satellite test.This thesis analyzed the requirements and techical indicators of payload dataloader firstly, and determined to choose the PXI&PXIe as the system structure ofsatellite payload data loader. Then, based on the concept of hierarchical test andmodular design, we proposed the overall design plan. According to storage capacity,interface type, mechanical dimensions and some other factors, functional moduleswere divided. Satellite payload data loader used FPGA as the core controller ofeach module, and used flash array as the storage solution of high speed payloaddata simulator, which achieved a single-channel storage capacity of32GB, a single-board storage capacity of128GB, peak reading and writing speed of over85MB/s.Using CF card as the storage solution of low speed simulator, single-channelstorage capacity were over8GB. Using isolation chips based on capacitive isolationtechnology, the problem had been solved that high speed parallel data was receivedmistakely because of the delay mismatch of channel to channel and chip to chip.The transmission rate of syncgronous LVDS signals in the design is up to300Mbps.The thesis also improved the traditional algorithm of frame and schedul based onCCSDS AOS protocol, combinated the virtual signal path scheduling method ofremaining data volume and signal path priority, the data downlink rate was steadyat605Mbps while the payload data framing module simulated the real satellitepayload data processor well and the integrity of data packet were ensurd. With thegigabit ethernet transmission technology based on embedded system of Power PC, satellite payload data loader sent multi-channel high speed date streams to theground server through the network. The speed of single ethernet port was steady at320Mb/s. Finally, we designed the control software by LabWindows/CVI whichcoordinated with the hardware to achieve the fuctions of payload data loader.Satellite payload data loader itself can build a closed-loop system. After a longtime and multi-angle test, the quality of LVDS and RS-422signals reach thestandard, the perfprmance of memory is satisfied, and there are no error bit of everypayload channel. Satellite payload data loader fully meets the requirements and hascompleted the electrical performance test coordinated with a certain satellite datatransmission system. It will play a greater role in the test of the satellite’s othersubsystems.