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1553B Bus Controller Design Based On FPGA

Posted on:2015-02-01Degree:MasterType:Thesis
Country:ChinaCandidate:J ZhaoFull Text:PDF
GTID:2268330428958873Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
The gesture control systemof various kinds of flight equipment,like human’s hands andfeet, controls the attitude of the flight.The controllingcomputerin the gesture control systemisresponsible for command and datadelivery, it is the brain of the whole system.For the currentwidely used1553B bus protocol, the controlling computer can not meet the communicationdemand.To address this issue,1553B bus controller which is the repeater between thecontrolling computer and RT terminal is designed in this paper, reliable communicationbetweenthe control computer and RT terminal is realized.RS-422interface is used tocommunicate withmissile-borne computer, the fast configuration of1553B protocol chip isrealized using FPGA internal IP core, data communication between missile-bornecomputerand RT terminal is designed reliably.RS-422interface is applied as a transit interface to solve the problem which is theinterface mismatch between the control computer and the RT terminal. The method ofdividing the clock to control the baud rate of the serial data is applied in this paper.Whenusing this method to control the serial data read point,the read point is close to the middleposition of each data bit,so as to avoid errors arising from the dither signal,and to avoiderror-reading due to the inaccuracy of the data pulse width.Protocol chip BU-61580is used to achieve1553protocol. As BU-61850can work in BC,RT and BM modes, each mode must be configured according to the actual needs, dozens ofregisters are needed to configure in each mode. To simplify the logical design, BU-61850isquickly configured, internal IP corein FPGA is applied in the design,the configurationinformation is stored in the ROM in advance,and configuration information is written in theBU-61580before the power turned on.So the length of the software is greatly shortenedand inthe mean time, the configuration parameters are more convenient to modify.In addition to complete the basic functions like data forwarding and data amount control,as a part of attitude control system, reliability design of bus controller must be focused. Ahardware platform is built in hardware design in the principle of simplifying circuit to reduce the failure degree. Erroravoidance design and error checking design are emphasized in thisdesign to improve the data transmission reliability in software design.Erroravoidance designruns through programming and it is a basic principle that programming must comply.Errorchecking design is implemented in the data transfer process for each functional module;allaspects of data transmission are checked at each level to ensure that no errors occurred in datatransmission.1553B bus controller mentioned in this paper has passed all kinds of tests; hardwarefailure and logical dysfunction are not occurred in the test, so the design of the bus controlleris proved to be reasonable and reliable.
Keywords/Search Tags:RS-422interface, 1553B bus, FPGA, BC mode, Reliability design
PDF Full Text Request
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