Design And Implementation Of A High-Efficient 1553B Bus Controller Based On FPGA

1553B bus has the advantages of high reliability,high real-time performance and fast transmission rate.Therefore,the bus is increasingly used in domestic military,aviation and aerospace fields.At present,the 1553 B dedicated chip from Data Device Corporation is commonly used in implementing the 1553 B bus protocol in the country.Although the dedicated chip can implement the function of the bus controller,it is not flexible to handle messages.Its efficiency is low because it needs to be matched with the master control chip to deal with the abnormal state.Therefore,this paper expands the function of bus controller based on the 1553 B bus protocol and designs a high-efficient bus controller of 1553 B bus.Firstly,to solve the problems of high cost and large occupation area when using the 1553 B dedicated chip to achieve multiple dual-redundant 1553 B channels,by analyzing the internal working principle of the dedicated chip,combining with the functional requirements,selecting the components with the same function to replace its internal transceiver and designing the internal logic and interface control of the bus controller,this paper proposes a dual-channel design scheme with the cost not higher than that of the dedicated chip.This design implements dual-channel 1553 B bus protocol based on FPGA and reduces the occupation area of the chip and the communication cost of 1553 B bus.Secondly,aiming at the low efficiency of the 1553 B dedicated chip in dealing with the the abnormal state,by analyzing the internal message processing mechanisms,this paper improves the execution sequence of messages on the original rules and proposes a highefficient design of bus controller.This design judges the abnormal state based on different message modes and automatically chooses messages to be executed,which reducing the response time and satisfing the requirements of the fast response and the pretreatment.Finally,this paper establishes the validation methods and process of high-efficient 1553 B bus controller based on FPGA,tests the correctness and efficiency of the design by function simulations,verifies the communication effect by intermodulation experiments between two cards and implements the function of the fast response and the pretreatment against the abnormal state.In the end,the test results show that this design's response time against the abnormal state is stabilized within 5?s.Compared with the fast response design based on host computer software,the execution efficiency of emergency messages in this design was increased by 62%.This design's product has been delivered to the research institution and put into use.