1553b Bus Interface Fpga-based Design

MIL-STD-1553B is a time division, command/response, multiplex serial data bus standard. It is the best solution of aircraft equipments connecting because of its high reliability and flexibility. Now it has been widely used in plane, warship, tank and other civil area. The key component in the 1553B bus system is the bus interface chip.After studying the protocol of MIL-STD-1553B and some chip designs of foreign companies, combining the EDA technology, this paper puts forward a project which integrates the bus interface blocks in a FPGA. After introducing the bus interface blocks like Bus Controller and Remote Terminal, this paper shows the detail structure of the Bus Controller module and Remote Terminal module. The two kinds of bus interface blocks have been integrated in a XILINX Virtex-4 series FPGA.At last, the design has been verified and simulated on the FPGA function board. The result of the testing shows that this design can act as a BC or RT. It can deal with the messages transferred on the twisted bus. So this design method is reasonable and can be realized.