Design And Validation Of A TTP/C Bus Controller Based On FPGA

Open electronic controller with specialty of highly modular, high reliability, easy maintenanceand low cost of the entire life cycle, is one of the future directions of the aero-engine electroniccontroller. Fault-tolerant data bus is the key technology to realize the electronic controller. This paperfocused on design techniques of the TTP/C bus controller, and based on which, open electroniccontroller experimental validation was carried out.On the basis of TTP/C protocol basic architecture and bus operation mode, TTP/C bus controllermodular structure diagram based on FPGA was given, which was divided into the physical layer, datalink layer and protocol service layer. The key parameters of the TTP/C bus controller were determined.The bus driver, bus transceiver, BG unit, MEDL list unit, time triggers, CNI interface, membershipconsistency algorithm and global synchronization clock module were designd respectively.A dual-channel TTP/C bus communication test platform was established. Multi-node datacommunication tests showed proper functions of all nodes, with no packet loss or error. A faultinjection module was accomplished thus multiple failure modes fault injection tests was carried out.The results indicated that all single-channel faults were tolerant, and all dual-channel failures could bedetected by the bus controller.Finally, a fault-tolerant open electronic controller was built with two input nodes, three controlnodes and two output nodes.The PIL Simulation tests of the open electronic controller was carried outwith a turbofan engine model as the controlled object, and the state-regulation control ability of thecontroller was validated. By fault injection to the nodes, the reconfigurable capability of the controllerwas also validated.