Development Of Distributed Fault Recorder Based PCIE Bus

With the construction of a strong smart grid, fault recorder has played anincreasingly important role in finding the cause of the malfunction and failureanalysis. Improving existing fault recorder to play a more excellent role is of greatsignificance.This paper summarizes the dynamic study of fault recorder at home andabroad, points out the current problems, and proposes a distributed fault recorderbased on PCIE bus associated with the state’s technical specifications and designrequirements. Then introduces the hardware structure of the system, especiallydata acquisition system based on PCIE bus, and describes in detail in the text ofthe model and the characteristics of each circuit chip.The paper also summarizes the algorithms used in the fault recorder,including starting algorithms, fault-election phase, fault location, transformeranalysis algorithms. Fault location algorithm which based on distribution linemodel, has been greatly improved in accuracy compared to conventionalalgorithms based on lumped parameter model; in addition, the paper proposes analgorithm which can identify transformer pinout fault types, we can find out thefault voltage level and fault phase where fault happens.At last, the paper raises the overall software design of the fault recorder, adetailed description of the software for three functions and structure of each majorsection is completed.