A Study Of Low Dropout Linear Regulators With High PSRR

The expansion of portable electronic products, such as mobile phones, MP3, ipad,power management chip’s research and development are increasingly becoming the focus.Among them,because LDO has small volume, less peripheral circuit, without a ripple,EMI etc, it is widely used.In RF circuit,the hybrid circuit of digital and analog and the technology of SOC, the influence of power supply’s faint noise will be more prominent.Therefore, designing a LDO circuit with high PSRR has extremely practical significance.The purpose of this paper is to design a LDO circuit with high PSRR,applied in CDMA mobile’s ratio frequency circuit.Firstly,Paper discussed three ways of power supply noise spreading,namely the bandgap module introducing the noise and error amplifier module introducing the noise and the power level introducing noise,and discussed the mechanism of introducing noise in the three ways.Based on this,in view of the power stage circuit,adopting the technology of feedforward ripple elimination,restrain the introducing noise of the power level’s limited output impedance rds and negative feedback loop’s vgs;In view of the bandgap reference module circuit,adopting voltage’s regulation technology,restrain the introducing noise effectively;In view of the error amplifier module circuit, the use of two-level error amplifier with N- DA + P- CS combination,improve the power supply rejection capability effectively. voltage In the low frequency, PSRR need to be the value of 75 dB;And in the high frequency, PSRR need to be the value of 50 dB at least.Its input voltage’s range is 3 ~ 5V.The output voltage is 2.8 V.In addition, in order to guarantee the chip working properly,other auxiliary circuits of over temperature protection, over current protection and short protection are added to it.Finally the work is circuit’s design and simulation based on 0.5μm N-well process of CSMC.In the condition of tt in process Angel,normal temperature,5V’s power supply voltage,10μF’s load capacitance,the writer design and simulation the circuit.The simulation results show that the minimum pressure drop Vdrop is less than 200 mV;under the condition of 200mA’s load current the static current Iq is about 116 μA;the SV is about 0.05%;the SI is about 0.15%;Under the low frequency, RSRRLDO is more than 80 dB;When frequency is between 1 KHZ and 10 KHZ, RSRRLDO is more than 50 dB.The result shows that the design has better performance.