Research And Design Of Low-Dropout Regulator With Low Noise And High Power-Supply Rejection Ratio

In the 21st century,the application of information technology has developed rapidly.Consumer electronics,automotive electronics,industrial electronics,and medical electronics markets are becoming more prosperous,and power management chips are getting more and more attention.LDO,which have the characteristics of low cost,low noise,and fast response,have become one of the power management chips with the largest market share.As the feature size of semiconductor manufacturing processes continues to decrease,system-on-chip integration is higher and faster.The voltage required by the system will be lower and the signal amplitude will be smaller,which makes the signal more susceptible to noise interference.Therefore,as a power supply,the noise suppression of LDO becomes an aspect that must be considered in the circuit design.Based on this,this article designs an LDO with low noise and high PSRR.The main research contents of this paper are as follows:（1）The device noise and LDO circuit noise are analyzed,and the low noise LDO is designed.This paper analyzes the source of noise and compares the characteristics of different types of noise.According to the noise type,the noise suppression method and its influence on other performance parameters are analyzed.The output noise expression of LDO is obtained by noise analysis.In this paper,the noise reduction port circuit and feed-forward capacitor module are used to suppress the noise in different frequency bands,to improve the noise performance of the circuit.（2）The PSRR of LDO is analyzed,and the LDO with high PSRR is designed.This paper analyzes the PSRR of the LDO circuit system,obtains the PSRR formula of the LDO,and determines the design idea of high PSRR circuit.The power suppression performance of LDO in different frequency bands is analyzed,and the influence of different module circuits on the power performance of the whole circuit is obtained.The power suppression performance of the basic amplifier structure which may be used in the error amplifier of the LDO is analyzed.And the design of the error amplifier is realized by using circuit structures with good power suppression performance.（3）In Cadence Virtuoso simulation software,LDO with low noise and high PSRR is realized based on BCD 0.18μm process of DB Hi Tek company.The LDO can work at-40 125℃,with a wide input voltage range（1.4-5 V）,wide adjustable output voltage range（0.8-3.95 V）,large load current（2 A）,low dropout voltage（125 m V）,low noise and high PSRR performance.The simulation results show that the root mean square of the noise of the LDO is 8.42μV_{RM S} when the input voltage is 3.3 V,the output voltage is 3.3 V,and the load current is 1.5 A.And the PSRR of LDO at 1 MHz is more than40 d B when the output voltage is in 0.8 3.95 V and the load current is 0 2 A.Compared with other published LDOs,the LDO designed in this paper also has good load regulation rate and linear regulation rate and has a very low figure of merits（0.07 m V）.