Research And Implementation Of Digital Phosphor Display Technology

As one of the most significant measure instrument for the electronic engineers, oscilloscope has become more and more important in the field of electronic measurement. Along with the gradually improving measurement requirements, better display details and higher waveform capture rate become the target of the oscilloscope.In the traditional digital storage display device, the high speed of data acquisition rate and the slow speed of display refresh rate form a contradiction. On the other hand, the digital storage oscilloscope could just have the distinction between "bright" and "black". Compare with analog oscilloscope, the digital storage oscilloscope missed many details on waveform and lack of the levels feeling of brightness. But for digital phosphor display technology, higher capture rate could be guaranteed. And also it can simulate the multistage brightness information, just like the electron beam hit on the phosphor screen of an analog oscilloscope. By using the technology, the digital oscilloscope's problem of long "dead time" and low capture rates could be efficiently resolved.The thesis studied the principle of digital phosphor display technology, and designed a scheme based on the waveform development, waveform elimination and three-dimensional cache to construct the three-dimensional wave in the FPGA. Combining with SPOC(System on Programmable Chip) technology, the paper designed a set of test system based on the structure of oscilloscope. The main chip of this system is a cyclone V series SoC FPGA. In this chip, FPGA and ARM CPU are physical independent. They are interconnected through the on-chip bus. Compared to the separated structure, the SOPC structure make the hardware much more simplified, and also the communication bandwidth and accuracy are improved effectively.The paper designed the three-dimensional waveform logic algorithm and realizes the functions includes trigger and cache of the acquisition data, develop and cache of the three-dimensional waveform, and the control of horizontal time base and vertical voltage gain. In order to realize the waveform elimination and color transformation, the paper designed the self defied module named Color Transform. And Designed the module named Function Control to set the parameters of the FPGA modules. Both of the self defied modules meet the Avalon Memory MAP standard. Combined with the official IP library, a Qsys subsystem is constructed based on the ARM hardcore CPU. Using embedded Qt platform, designed the waveform display and the interface to set the parameters of the FPGA parts. According to the requirements of input signal dynamic range and other factors, designed the analog channel circuit. The analog channel composed of attenuation network, impedance matching circuit, controllable gain amplifier network and A/D sampling circuit. The function of the analog channel is to implement signal conditioning.According to the test, the waveform capture rate of this system can be over 70,000wfms/s. This system could be used to observe some transient signals, which were hard to be seen in traditional methods.