Research And Application Of VMM-based Coverage-Driven Verification Methodology

As the scale and complexity of Integrated Circuits increase gradually, the verification also becomes more and more difficult. According to incomplete statistics, the verification time accounted for the entire product development cycle of about 75%. Depend only on the coverage of a single authentication method, such as code coverage verification, functional coverage verification, assertion coverage verification, is not satisfied the requirements of Integrated Circuits. Therefore, the research of verification method has highly value to study and extremely important for practical significance.Based on VMM verification platform, this dissertation mainly uses hardware design and verification language SystemVerilog, focusing on the research of Coverage-Driven Verification methodology, and built it to verify the Multifunction Vehicle Bus Controller (MVBC).Firstly, the research of the Coverage-Driven Verification methodology in recent years was analyzed and summarized. Then, the principle of Coverage-Driven Verification methodology was simply elucidated and analyzed. The paper compares the difference characteristic the VMM verification platform and the tradition verification platform.Secondarily, based on the verification methodology of VMM, the principle of Coverage-Driven Verification methodology was deeply elucidated. Then, discuss the implementation process of code coverage, functional coverage model building mechanism and response checking mechanism of the Coverage-Driven Verification methodology. Lastly, we proposed method of extraction and how to cover the point coverage attribute relationship by analyzing the functional coverage to build a more complete model.Finally, the use of System Verilog hardware design and verification language, in the VMM verification platform, using Coverage-Driven Verification methodology to complete the verification of the MCU in MVBC, the establishment of functional coverage models and run it on the simulation tool VCS, validation of the thesis validity and accuracy of simulation. The analysis of the results shows that the verification of this article is effective to reduce the cycle of verification, improve the efficiency of verification, and ensure completeness for verification.