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The Design And Implemention Of The Acquisition System Based On Gigabit Ethernet

Posted on:2017-03-08Degree:MasterType:Thesis
Country:ChinaCandidate:Y B DingFull Text:PDF
GTID:2348330518496543Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
In digital communication systems,acquisition and transmission of high-speed data sources' signal is basis for the work of the whole system.High-speed acquisition system is designed to focus the process of storing and transmitting the collected data.It is responsible for collecting the source signal and transmitted to other systems and has a very important position.This paper which is based on the task of transponder system development designs the acquisition system based on Gigabit Ethernet transmission.This paper uses Altera's FPGA products as the CPU to design the circuit board.With the software simulation and actual on-board test,it completed the IP interface program of DDR2 memory chips and Gigabit Ethernet MAC layer,and finally realized processes from acquisition to the cache and then transmission.The paper has completed the following work content:1)Investigate the requirements of this application.Research the key technologies to complete this project and select chips from different types.Select EP3C25F324 of Altera as CPU,MT47H16M16 as DDR2 SDRAM and 88E1111 of MARVELL as PHY chip of Gigabit Ethernet.2)Design and finish the acquisition system hardware circuit.This paper investigates the operating parameters of the various components.It understands the key of the various parts of the circuit and simulates the analog filter.In the meantime,it makes the PCB package of all the components and PCB layout based on the component chip manuals.Finally,it completes the PCB board and implements hardware basements of the acquisition system.Paper gives the acquisition system's major circuit schematic and whole PCB diagram.3)Design and write software code for the acquisition system.Firstly,it simulates the DDR2 and Gigabit Ethernet MAC IP core and understands how they work.It further designs and simulations IP interface program to achieve the overall data path.Then,paper models the AD chip and DDR2 chip through Verilog HDL behavioral language.Finally,it uses Modelsim to do the functional simulation for the FPGA program.Article on each module has a detailed simulation processes and results analysis.4)Test the program of the acquisition system.Download the software to the FPGA,to do the hardware on board tests and catch the key signals.Paper gives the results and the RTL-level circuit diagram synthesized by the Verilog HDL.It catches the waveforms of the system and analyzes them to get the conclusion.This paper accomplished the acquisition system based on Gigabit Ethernet.This system plays a role in the real project,and leaves the expansion interface for blow applications.
Keywords/Search Tags:acquisition system, bus, FPGA, Gigabit Ethernet, DDR2
PDF Full Text Request
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