Hardware Acceleration Of Feature Extraction Algorithms For Pulse Signal Based On FPGA

In modern particle physics experiments,the analysis and discrimination of physical events depends on the observation of the types and kinetic information of the final state particles.This information is usually extracted by measuring the energy,time,and position of particles in the detector.Due to the exponential signal and the non-Gaussian noise of the detector system,the traditional methods is hard to achieve optimal accuracy and efficiency.Recently,the neural network has been successfully applied to high energy physics for data processing.Because of the large amount of calculation of neural network,to meet the requirements of fast and real-time data processing,hardware accelerator is needed to accelerate the calculation of the neural network.At present,there are many researches on the extraction of pulse parameters at home and abroad.Common methods include curve fitting,Gaussian filter shaping,triangular filter shaping,etc.There are also some methods based on machine learning,such as methods based on LSTM model and population genetics algorithm.However,most of these studies are used for offline data analysis.With the development of high energy physics experiment,the scale of the experiment and the amount of sample data is gradually increasing.It is an important research direction to preprocess the data in the detector front-end electronics and reduce the off-line storage of experimental data.In this paper,a deep learning network model is designed based on the denoising autoencoder model,which is used to extract the pulse time of one-dimensional time series.Based on this network,a neural network accelerator based on FPGA is designed.The accelerator is reused in every layer of the network to complete the inference of the neural network.Under the analysing of the parallelism and the memory access of data in convolution operation,a variety of parallel methods are used in the design of the accelerator to balance computing resources and efficiency.A strategy of high data reuse is adopted to reduce the memory access cost of feature map,kernel and partial sum in the multiply-accumulate calculation,so as to improve the calculation efficiency and reduce resource and energy consumption.In the specific calculation,the operations are distributed to multiple arithmetic logical units and a combination of spatial adder tree and temporal adder tree to complete the calculation of the convolution layer,deconvolution layer and fully-connection layer.The test result shows that,the peak operation performance of the accelerator reaches 1.665GMAC/s at 25MHz.Under 8 bit fixed-point quantization,the time resolution of the pulse time estimated by this accelerator is 0.01437 ?s.This design provides a possible way for real-time data preprocessing in the front-end electronics of detectors to reduce data offline storage and improve the accuracy of pulse time extraction.It will be used in the readout circuit of the calorimeter in the high energy physics experiment.