Research On Hardware Acceleration Of FDTD Based On FPGA/PULPino SoC

The finite difference time domain（FDTD）method is one of the widely used techniques in numerical simulation methods for solving different electromagnetic field problems.Reverse time migration（RTM）imaging can accurately attribute the wavefield to the real subsurface spatial location when dealing with steeply dipping structures and complex velocity models,which is widely used in geological exploration,petroleum and natural gas detection and other scenarios.Therefore,the introduction of RTM imaging method in electromagnetic imaging based on FDTD method can achieve better imaging results.However,when the FDTD method is traditionally implemented based on CPU running high-level languages,its computational efficiency depends on the operating system,the compiler and the size of problem space.It will cause cache misses during the calculation process that the large number of memory access attempts.Thereby the performance of the overall system is degraded.This paper designs a 2D FDTD two-dimensional FDTD accelerator based on FPGA to solve the problem of slow FDTD computation,and further implement a faster RTM acceleration circuit based on it.In addition,the FDTD hardware module is integrated into the open-source RISC-V PULPino SoC platform,which improves the computational speed of FDTD method.Specific research work are as follows:1.Research on hardware acceleration of 2D FDTD accelerator based on FPGA.The 2D FDTD algorithm is simplified by coordinate transformations.The data dependence is analyzed during the iterative update of FDTD method.And the calculation process is optimized based on FPGA using fixed-point data format,pipeline,parallel computing,etc.The 2D FDTD accelerator is implemented with truncated boundary as second-order Mur absorption boundary condition.The experimental results show that the accelerator running at 100 MHz is 7.59 times faster than the computation speed of a PC with a main frequency of 3.6 GHz.2.Research on the hardware acceleration of electromagnetic wave RTM imaging based on FPGA.The RTM parallel computational circuit with simultaneous computation and storage are designed based on a 2D FDTD accelerator.The crosscorrelation imaging calculation circuit is designed by using resource sharing and pingpong operation technology.Compared with the calculation speed of 3.6 GHz PC,the forward process calculation speed of 100 MHz RTM acceleration circuit is improved by 17.37 times and the backward process is increased by 18.40 times.The completion time of cross-correlation imaging is 2.34 times slower than PC,while the clock frequency is 1/36 of PC.3.Research on hardware acceleration of FDTD method based on the open-source PULPino SoC.Simplified iterative updating equations for FDTD.Based on the opensource platform,the FDTD calculation module is integrated,which uses AXI bus to read and write electromagnetic field-value data in parallel.The hardware and software co-simulation environment is built to perform functional simulation verification of RTL design.The experimental results show that the calculation speed of SoC at 25 MHz is1.58 times faster than the 3.6 GHz PC,and the clock frequency is 1/144 of PC.FPGA is used to verify that the RTL design is consistent with the simulation in the real circuit.