High-speed Analog Multi-channel Design Based On SDD Detector

In the fields of nuclear science and technology,space exploration,mineral resources exploration,and environmental radiation monitoring,silicon drift detectors(SDD)are widely used due to their superior detection performance,especially at high count rates its performance is more prominent.The silicon drift detector has the characteristics of extremely small equivalent output capacitance of the output electrode,short charge collection time and high signal-to-noise ratio of the output signal.Therefore,a high energy resolution can be achieved under conditions of high counting and short shaping time.In order to make full use of the superior performance of silicon drift detectors,the use of high-performance multi-channel pulse amplitude analyzers(MCA)is particularly critical,but currently used analog multi-channels(AMCA)and digital multi-channels(DMCA)each have advantages and disadvantages,and they cannot fully exploit the advantages of silicon drift detectors.Thence,according to the characteristics of silicon drift detectors,based on the traditional AMCA,combined with DMCA design principles,the high-speed AMCA for silicon drift detectors are designed.The high-speed AMCA have the advantages of DMCA,such as anti-stacking,low pulse loss rate,high pulse pass rate,and high energy resolution,at the same time the advantages of AMCA low power consumption,low cost,high stability and low line noise are also taken into account.This research comes from The National Key Research and Development Program of China “High-Resolution Airborne Gamma Spectrum Measurement and Airborne Imaging Spectroscopy Technology”(NO.2017YFC0602100)and National Natural Science Foundation of China “Nuclear Pulse Signal Chain Mathematical Construction and High Speed Real-time Research on Digital Reconstruction Technology(No.41474159).The high-speed AMCA for silicon drift detectors designed in this paper,the main results of the research at this stage are following.1.In order to make the high-speed AMCA designed in this paper have a high pulse pass rate,a high-speed,low-noise analog front-end circuit using a high-speed S-K filter and a high-speed operational amplifier to achieve a width of 1.3uS and a rising edge of 350 nS Gaussian are designed in the paper.The design goal of pulse signal output can reduce the pulse accumulation and increase the pulse pass rate under the condition of high counting rate.The high-speed peak sample and hold circuit is designed with the ADA4817 high-speed operational amplifier JFET with a bandwidth of 1GHz,which can achieve 350 nS rise time.Fast peak sampling and hold of Gaussian signals.2.Based on the new 5Msps high-speed SAR ADC and FPGA fast sequential logic design to achieve only 0.5uS pulse peak sampling,much smaller than the traditional AMCA dozens of us,significantly reducing the AMCA dead time.3.In the fast channel,a fast deconvolution circuit is used to deconvolute the analog front-end output pulse signal to obtain a very narrow fast-channel trigger signal.The output pulse width is only 350 nS,the rising edge is as low as 50 nS,and the input signal is 200 kHz and 2V.There is no obvious overshoot under the conditions,so the peaking effect of the multi-channel system can be significantly reduced,thereby reducing the chance of accidental pulse loss.4.Using the MAX10 series of FPGA chips to complete high-speed AMCA timing control and ADC discretization data high-speed acquisition,transmission,MAX10 series is Intel's low-cost,high-performance,small-size,low-power FPGA,internal continuous distribution The wiring structure makes it faster and timing delays predictable.5.Combined with DMCA fast channel design,through the threshold comparison method to determine the presence of pulse,and through the adjacent pulse trigger time to determine whether the accumulation of pulses,can further increase the number of analog multi-channel count rate,reduce dead time;The FPGA chip acquires the trigger signal of the fast channel to control the analog switch to switch the input signal of the ADC to the baseline and acquire the amplitude of the baseline signal in real time,thereby solving the problem that the traditional AMCA cannot accurately estimate the baseline.6.Through the high-speed peak sampling and holding circuit to obtain the pulse amplitude,reduce the noise of the ADC discretization data,improve the accuracy and consistency of the ADC acquisition data while reducing the FPGA algorithm complexity,and then it can achieve high energy resolution,low power consumption and high stability design requirements.7.From the power supply structure design,PCB layout and routing,chip selection,device parameters and other aspects to achieve a wide range of input voltage,low ripple noise,anti-interference ability of the design goals,and only DC-2.5 interface can achieve power supply and support the power supply range of 7.2V ~ 23 V.