Research Of Ultra-Low Noise,High PSRR LDO Regulator

Voltage regulator can maintain circuit voltage at a specified range.It is an essential component in power source of integrated circuit.The device in the circuit could be damaged with excessive voltage,while too low voltage can lead circuit malfunction.In addition,some circuit with wide working frequency,such as PLL,clock generate circuit and digital analog converter with high speed and accuracy,are sensitive to power noise.The performance of these noise-sensitive circuit will be degraded with high power noise.Therefore,a “clean” power source is desirable for such circuits,which has small noise and keep high PSRR at wide frequency range.Traditional ESR compensation can’t satisfy the requirement of recent circuit design.A novel frequency compensation is required to ensure the system stable under different loading condition.Thus,it is important to design a LDO regulator with ultra-low noise,high PSRR.LDO’s noise source is analyzed.In order to reduce LDO noise and save chip area,a pre-regulation and low pass filter structure of LDO is used and the LPF is optimized.Besides,the ripple transmit path of the LDO is discussed and the method of feed-forward ripple cancellation is presented.We insert a feed-forward path between the drain and gate of the PMOS power transistor to induce power ripple into power transistor gate.This method can keep the voltage between source and gate of power transistor free from input ripple.In the meantime,the PSRR of the LDO is improved and high PSRR can be retained at a wide frequency range.Finally,a novel compensation method is deployed to improve traditional one.In this method,an emulated ESR zero is generated in the transfer function to compensate the effects of the unwanted pole in the transfer function and improve the stability of the LDO.In this work,the proposed circuit based on 0.18μm CMOS process is simulated with Cadence Spectre.The result shows that this LDO can keep 2.39μV rms integrated input noise with frequency range varying from 10 Hz to 100 kHz.The PSRR is about 97 dB at low frequency and 62 dB at 1MHz.The system can keep high stability with enough phase margin,no matter under light and heavy load.Otherwise,bandgap and support module exhibit high performance and the designed LDO satisfy the design requirement.At the end of this thesis,the cautions of the layout are demonstrated,and the layout is completed.