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Design Of 1553B Bus Interface Compatible With JBU64843

Posted on:2020-09-16Degree:MasterType:Thesis
Country:ChinaCandidate:C HeFull Text:PDF
GTID:2392330590494957Subject:Microelectronics and Solid State Electronics
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With the rapid development of the aerospace industry,the number of devices in the aircraft continues to increase,and the connection system is more complicated.The way of connecting with ordinary cables can not meet the real-time requirements and reliability.Therefore,the United States proposes the signal multiplexing method and releases the MIL-STD-1553 B protocol.The 1553 B bus uses a dual-duty bus system,which greatly improves the reliability of data transmission on the aircraft.The most critical part of the 1553 B communication system is the interface chip.Therefore,it is very meaningful to study and design the 1553 B interface.This paper deeply analyzes the functional specifications of the JBU64843 chip,according to the design requirements,the top-down design method is adopted to design the 1553 B bus interface of BC(Bus Controller)and RT(Remote Terminal).Design double-buffered data management structure,realize memory management of BC and RT,automatically switch to redundant bus when message transmission fails,transmit information to CPU through interrupt,speed up processing of error message;For different message transmission formats,the lookup table mechanism is used to increase the addressing speed of message blocks;The state machine control logic is used to design the protocol analysis unit to analyze the MIL-STD-1553 B protocol;In order to reduce the burden on the CPU,the frame automatic repeat mode is designed,and BC can automatically process multi-frame messages;The loop buffer structure of the RT is realized,and the capacity of the message block is set by programming,which is suitable for message transmission of different data amounts.All features included in the design are compatible with the JBU64843 chip.This paper uses the Verilog HDL programming language to perform RTL modeling of the 1553 B bus interface,and build a 1553 B bus system with one BC and three RTs to perform functional verification.The simulation results show that basic data transmission,broadcast format and multiple modes of commands can be realized between BC and RT,RT and RT.The mode commands include returning the previous status word,returning the previous command word,resetting the remote terminal,etc.It can implement various interrupts such as command stack overflow,RT loop buffer overflow,BC frame end,and message end.Response time validity,word count,parity,and various messaging errors can be detected.
Keywords/Search Tags:1553B bus interface, BC, RT, memory management
PDF Full Text Request
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