Research And Design Of Sink/Source Fast Transient Response LDO

In recent years,the memory industry has developed rapidly.The storage space of DDR memory is gradually increasing with the input power supply voltage decreasing.The clock frequency and data transmission rate are also accelerating,and the requirements for the SSTL interface protocol are getting higher and higher.For memory power applications such as DDR,DDR2,DDR3,DDR3 L,LPDDR3,DDR4,etc,power supply with strong load capability,high output accuracy,good transient response characteristics,and capable of Sinking/Sourcing load is required in the power management chip.LDO linear regulators have the advantages of small output ripple,fast response,high output precision,simple structure and low cost,and become the first choice for DDR memory power supply.The LDO linear regulator chip — XD1997 is designed in this paper,which combines Sink/Source capability and fast transient response.The chip is powered by dual supply voltages,and the internal input voltage can be as low as 2.5V.A 20?F output capacitor is required for fast transient response speed;the output stage highside and lowside power transistors are NMOS push-pull outputs that can Sink/Source 3A load.The designed error amplifier adopts a symmetrical form of OTA structure.The multi-channel current mirror structure makes the error amplifier output a low-impedance node and the pole is at high frequency.The high output slew rate improves the transient response speed of the LDO.The large Gm increases the LDO gain and bandwidth.The whole system is a Gm-driven singlepole system.In addition,a quiescent current control circuit is designed to ensure a large current flow during no-load.The output voltage REFOUT of the voltage buffer is applied to the reference under various DDR conditions,which can realize the Sink/Source 10 m A load,and use the translinear theory to set the quiescent current of the voltage buffer output stage.The combined zero of the Sink/Source variation is generated by the compensation circuit to realize the loop stability of the Sink/Source current.Symmetrical soft start and overcurrent limit circuits can be realized at Sink/Source,and the overcurrent limit level becomes half of normal when PGOOD is abnormal.The PGOOD control output circuit can detect the change of the output voltage in real time.When the output voltage is not within the window of ±20% the reference voltage,the PGOOD signal is pulled low.The circuit integrates the OSC module to achieve a 2ms startup delay,which can precisely control the start and stop of the PGOOD signal.This paper is based on the 0.35?m BCD process and is simulated using Cadence's spectre simulation software.The results show that the LDO uses dual power supply technology for various DDR memory power supplies.The push-pull output can achieve Sink/Source 3A load,and the output voltage changes only 20 m V when the load changes from-3A to 3A,the load regulation rate is 0.26%/A;output voltage overshoot is only 19 m V when the output current is from-1.5A jump to 1.5A with 3?s rise time,and 2.3?s resumes normal output;the maximum drive load of the voltage buffer is ±40m A,and the output changes only about 2m V when the load changes from-10 m A to 10 m A.The static power consumption is only 0.18 m W,and the simulation results meet the design requirements.