Design Of A High-temperature CMOS Low-dropout Linear Regulator

In recent years,with the rapid development of modern technology,due to higher requirements of high temperature electronic devices,more and more attention has been paid to high temperature microelectronics.In view of the rare research situation of low dropout linear voltage regulator(LDO)in bulk silicon CMOS process which can work in high temperature,the temperature characteristics of bulk silicon CMOS components were studied from the aspects of the carrier concentration,mobility and reverse leakage current of the PN junction.The thesis designed a LDO which can operate in temperature range from-55? to 210? in a bulk silicon CMOS process,based on the method of leakage current balance compensation and the theory of zero-temperature-coefficient gate bias voltage point(ZTC point).The main work of the thesis is as following:The thesis analyzed the characteristics of MOS transistors at high temperature,and studied the related estimation methods and quantitative calculation formulas of various parameters of CMOS device.Combined with the theory of ZTC point,the conditions that should be satisfied at ZTC point of MOS transistors and the temperature characteristics at that point was also analyzed.Based on the Kirchhoff's Law,the method of compensating the leakage current at high temperature is researched.The parameters setting rules and leakage current compensation method of high temperature analog circuits were proposed,and then a layout design method suitable for high temperature work was worked out.The leakage currents in each voltage node were well matched and the sum was close to zero by properly configuring and compensating the sizes of the transistors.A reference current source with zero temperature coefficient was generated to provide the bias currents for other branches.Furtherly the zero-temperature-coefficient point parameters or voltage biases of the MOS transistors were dedicatedly set up for the key nodes with the assitance of the simulator.A new compensation scheme of dynamic zero point with buffer stage was propsed to make the zero point dynamically follow the change of the output pole with the load current,forming an effective phase compensation for the LDO loop,which guarantees the good phase margin and the stability of the system.Based on a 0.5?m BCD process of CSMC,the thesis completed the circuit design,tape out and chip test of a high-temperature LDO.The simulation results show that the key parameters of the LDO meet the design requirements.It validates that the LDO has high output voltage accuracy,low temperature coefficient,and high power supply rejection ration(PSRR).Good phase margin in different load conditions was achieved which guarantees good system stability.Good load transient response and linear transient response were presented.The chip test data show that the LDO performances are basically consistent with the simulation results at high temperature and meet the requirements well.The adjustable output voltage is 1.2V to 3.3V and the maximum load current is 300 m A.It can work stably in a wide temperature range from-55? to 210?,and the typical temperature coefficient is 44ppm/?.The line regulation is 0.18%/V and the load regulation is 0.4%/A at 210?.The voltage drop with the maximum load current is less than 250 mV.