Design Of Linear Regulator With High-stability Using 40nm CMOS

The implementation of multiple power domains in system-on-chip has been a challenging but promising topic.Low-dropout linear regulator has become a research hotspot for power management applications due to its many advantages such as simple structure,low power consumption,strong power supply ripple suppression and fast load response speed.Even though the technology of LDO has been relatively mature,but for specific application environment such as So C system including voltage controlled oscillator,realizing low power consumption and small size of LDO,maintaining high stability in a wide range of load current and being able to respond quickly to load changes is still challenging.In this thesis,a high-stability linear regulator circuit used in a RF transceiver system chip is designed.The introduction of dynamic bias optimizes the impedance attenuation buffer based on parallel feedback technology,pushes the pole of the output power tube grid to high frequency,reduces the output resistance and reduces the quiescent current power consumption.A zero-pole tracking circuit is introduced for frequency compensation,then a dynamic zero is generated to offset the dynamically changing output pole,so a single pole within the unity gain bandwidth of the adjustment loop is realized.So that the LDO can achieve a phase margin of more than 65° in the entire range of the load current without using any low-frequency zero.It not only saves chip area,but also has good transient build-up behavior and small output voltage changes.The output voltage of this LDO can cover(1.17 V,1.43V).The final area is 388×380μm,and can provide up to 200 m A load current.This design uses Cadence Virtuoso for schematic and layout design,uses Spectre for prelayout simulation and post-layout simulation,and uses Calibre tools to complete physical verification and parameter extraction.The results of pre-layout simulation and post-layout simulation have a high consistency.Under the simulation conditions of process corner(tt,ff and ss),input voltage 2.97V～3.63 V,temperature-40℃～120℃,the simulation shows that the phase margin under light load and full load is above 85.34°,the quiescent current is less than 35.73μA,when the load current changes with 100 m A,the output voltage changes less than 41.94 m V.The tape-out test proves that the function is normal,the quiescent current is 53.8μA,and the load regulation is 0.096 m V/m A.