Design And Verification Of CAN Controller Based On 32-bit RISC CPU Core

Due to the distributed,networked structure and intelligent characteristics,Fieldbus technology saves hardware costs,installation costs,and space.Simultaneously,Fieldbus is more convenient for the maintenance of hardware devices and the compatibility of different manufacturers' hardware has also been improved.The anti-jamming capability of the system has led to widespread adoption in many automobile factories around the world.Controller Area Network(CAN)belongs to the Fieldbus technology and is now widely used in automotive communication and control systems.Then CAN bus can allow multi-node and multi-master communicate simultaneously.Traditional CAN communication usually consists of a MCU and a stand-alone CAN controller on a board-level circuit,but the board-level discrete system has certain flaws in real-time transmission and reliability compared to on-chip systems.To improve this point,this paper is based on the RISC CPU with MIPS instruction set,and researches the design and FPGA implementation of on-chip CAN controller.Based on the analysis of the mainstream CAN2.0B bus protocol,the hardware structure of the CAN controller is divided into several parts using a "top-down" approach,which mainly includes interfaces,register sets,transceiver buffers,bit stream processing control,bit timing control and error management.Then this paper will complete the design of each module circuit of the CAN controller with Verilog HDL hardware description language.Afterwards,Wishbone is used as the on-chip bus of So C system in this paper.In addition,the MIPS's interface,instructions,and data memory are implemented according to the Wishbone protocol,and the MIPS cross-compile environment is built based on Ubuntu.Finally,based on the hardware and software environment of the MIPS CPU,this article will reuse previous CAN controller and other IP to implement So C system to achieve CAN communication.After the design is completed,Verilog is used to set up the simulation environment for the CAN controller to perform functional verification.Then implement the Nor Flash and SDRAM controllers for the So C based on Altera's FPGA development board,and compile the entire So C system to download the configuration file to the FPGA chip through the Quartus II software of Altera.Finally,the So C system with CAN controller is implemented in the FPGA to communicate with the CAN controller on the market.The verification results show that the design of CAN controller can be compatible with the market CAN communication and the software and hardware environment of So C works normally.Therefore,wo can believe that the CAN controller meets the design requirements.This paper optimizes the stability and real-time performance of the board-level stand-alone CAN controller by the way of on-chip integration.The Wishbone bus is used to increase the portability of the CAN controller and the scalability of the So C system.The FPGA verification environment can provide reference to other projects,so this design has a good development prospects and engineering application value.