Packet-based transaction interconnect fabric for FPGA systems on chip

As the logic available in FPGA devices grows, traditional bus interconnects are struggling to keep up, and higher performance interconnects are required.;A prototype implementation is reported, describing the components that compose the interconnect, the interfaces between them, the algorithms used to assemble the interconnect, the development and testing methodology, and a proof of concept system.;Results show that for large systems, a Merlin interconnect provides higher frequency with less logic than the interconnect tools available from FPGA vendors. In addition, Merlin provides lower latency through the network than other FPGA NoC implementations, while costing less resources, at a higher frequency.;This thesis presents introduces "Merlin", a flexible, high performance, and light weight approach to on-chip FPGA interconnect, which includes a collection of packet based primitives, and a way to map transactions to packets, and algorithms for connecting components such that they provides the services required of a transaction interconnect.