Cost-performance optimizations of microprocessors

Fabrication technology scaling and design innovations have enabled microprocessor clock rate to double every 2.5 years and microprocessor integration level to double every 1.6 years. Conservative forward projections estimate clock rates of 3GHz and transistor counts of 520 million by the year 2009.; Sustaining these trends poses a multitude of challenges to designers. Among these challenges are the questions of (1) How to reduce both the design time and design cost? (2) How to formalize the architecture-level cost-performance tradeoffs and explore the expanding design space? (3) How to enable design reuse?; This research addresses these questions by formalizing the Par design concept, based on the Area-Time relationship of VLSI designs, to reduce the number of design iterations and to enable architecture-level cost-performance tradeoffs. Specifically, the Par design methodology helps designers stay on the Par curve consisting of design points that maximize performance under different area constraints. This research applies the Par design concept to two areas of increasing importance: the floating point unit (FPU) and the on-chip storage hierarchy.; High-level design tradeoffs require comparisons based on area and delay of the resulting design. This work develops models of area and delay that unifies the effects of both device and interconnect scaling. In addition, technology-independent area and delay models are derived to enable comparison that are not skewed by the effects of technology. Furthermore, we define a methodology for mapping these technology-independent design metrics of delay and area to specific process generations to define design/technology compatibility and to enable design reuse across technology generations.; Then, this thesis develops and applies FUPA, a FPU metric that incorporates four key aspects of VLSI system design: latency, die area, technology, and profile of applications. Using FUPA as a cost function, we classify the design space and define the Par curve of FPUs. These efforts cumulate in CFUPA, a FPU synthesis and guidance tool.; We continue by defining the Par curves of on-chip caches by developing CacheOpt, an on-chip storage hierarchy optimizer. CacheOpt automates the synthesis of an optimal cache hierarchy under area, I/O, and latency constraints with respect to a given technology and application batch. Applicability is demonstrated by applying CacheOpt to two applications of different requirements.