Research On Key Technologies Of Small High-speed Data Acquisition System

With the continuous improvement of the quality,efficiency and high-tech level of my country’s weapon equipment industry,its trend of intelligence,unmannedness,and systemization has become more obvious.The fuze is an important device to control the detonation of the projectile.The performance of the fuze system determines whether the weapon equipment can fully exert its effectiveness.Therefore,in the process of fuze design and development,it is necessary to conduct multiple test tests on the fuze.By collecting the fuze encoding signal,Analyze the signal characteristics as a basis for improving the design.The research of this paper is carried out in this context.Aiming at the new test requirements,it analyzes the shortcomings of the existing high-speed data acquisition and storage test system.Through the research on the key technologies of small high-speed data acquisition systems in special environments,a small high-speed data acquisition system is designed,which has the characteristics of adjustable sampling frequency,easy operation and strong versatility.This paper analyzes the domestic and foreign research status of high-speed data acquisition and storage systems.Starting from the relevant theories of high-speed data acquisition technology and high-speed circuit design,combined with actual fuze test requirements,a small high-speed data acquisition system design plan is proposed,and the key technology of the system function is analyzed,including time alternate parallel high-speed sampling technology,Impedance matching technology and anti-interference technology,etc.,and carry out system design through two aspects of hardware circuit and sequential logic.The system hardware circuit mainly includes sampling module,front-end matching module,FPGA module,storage module,power supply and clock module,USB module,etc.,using two AD9288 s to achieve three sampling frequencies of 100 MHz,200MHz,and400 MHz in a time-alternating parallel sampling mode,and sampling The frequency can be automatically matched according to different measured signals;anti-interference technology is adopted to optimize the design of power supply and clock circuits to provide a stable power supply and clock for the system;transmission line impedance matching technology is adopted to realize the signal integrity design.The related design was simulated through Cadence,and the correctness of the design was verified.The system timing logic is mainly the control logic design of FPGA,including high-frequency clock processing,high-speed signal acquisition,cross-clock domain storage,IP core calling,etc.Through logic design,the functions of each bottom-layer module are realized,and the top-level module is built to complete the systematic design.Finally,this paper analyzes the key logic of the system and validates it by simulation to illustrate the feasibility and deficiencies of the scheme design.The function of the small high-speed data acquisition system is verified through experiments,and the problems that arise are summarized based on the experimental results.Put forward specific suggestions for improvement.