Design And Implementation Of Fast Response Low Dropout Linear Regulator In High-precision Seismic Acquisition Station

In order to strengthen China's ability to extract local energy,the research and development of the front-end data acquisition unit of high-performance seismograph—the high-precision seismic acquisition station—is an urgent task.The high-precision seismic acquisition station includes many sub-modules,among which the power management chip is responsible for converting the external fixed power supply into a high-stability,low-noise,low-ripple power supply voltage and providing power for all other sub-circuits.Obviously,its performance has a great impact on the performance of the high-precision seismic acquisition station,so it is very important to develop a power management chip which is suitable for the high-precision seismic acquisition station.Low dropout linear regulator(LDO)has the advantages of simple external circuit,extremely low output noise and ripple,etc.It has became the better choice for power management chips in high precision seismic acquisition stations.In this paper,a systematic study of LDO is carried out.Based on the analysis of the working principle and different performance indexes of LDO,two LDOs have been designed and implemented with different circuit structures:1.The first is a traditional LDO with off-chip capacitance.A super class AB operational transconductance amplifier(OTA)is proposed as the he error amplifier for the fast transient response LDO,and its performance including dynamic response and AC characteristics are analyzed theoretically.It can be seen that the proposed circuit structure can realize large charging\discharging current at the gate of the power transistor,which not only make the LDO has excellent transient response performance and high power supply rejection ratio(PSRR),but also can ensure sufficient phase margin and load\line regulation.Therefore,the performance of the first LDO designed in this paper can be improved in all directions.The proposed LDO has been designed to a chip using SMIC 0.18?m CMOS technology.The experimental results show that under the premise of a load capacitor of 1?F and an edge time of 8ns,when the load current undergoes a 0-200 m A transition,the change in output voltage is 23 m V,and the measured PSRR is-74 d B at 1MHz.2.The second capacitor-free LDO adopts the adaptive biasing(AB)scheme.Based on the analysis of the different trade-offs between various performances in AB-LDO,a new circuit structure is designed to optimize these trade-offs.AB-LDO with recycle folded cascode(RFC)amplifier as error amplifier and cascode compensation as frequency compensation method can not only comprehensively improve the performance of the LDO,but also achieve maximum optimization of tradeoffs between different performance parameters.The proposed AB-LDO has been designed to a chip using SMIC 0.18?m CMOS technology.The experimental results show that when the load current jumps from 0.1 to 100 m A,the undershoot of the output voltage is 17.5m V and the overshoot is 13.5m V,achieving a high current efficiency of 99.93%.