Design Of Digital Input Audio Interface Circuit Based On S/PDIF

S/PDIF(Sony/Philips Digital Interface Format)is the abbreviation of Sony and Philips Digital Audio Interface.This interface standard was originally defined based on the AES/EBU standard,also known as the S/PDIF standard.This interface is widely used for its advantages of long-distance transmission,good compatibility,and low price.S/PDIF can transmit data streams of multiple audio formats.During long-distance transmission,the BMC encoding of the data frame allows the transmitting and receiving ends to complete the transmission with only one data line,and can ensure better synchronization.In addition,the BMC code can keep the average direct current potential of the transmission line close to zero,in addition to reducing power and reducing electromagnetic interference.However,the longdistance transmission of S/PDIF data will cause data damage.The single-ended synchronization mechanism used in its traditional design will result in a low synchronization error tolerance rate of the interface,and the decoding scheme based on the cyclic matching decoding scheme adopted in its decoding part will problems such as the large design comprehensive area affect the further application and development of S/PDIF in actual engineering.In view of the above problems,this thesis first analyzes the development status and research background of the audio input interface and S/PDIF standard,defines the basic product function design requirements according to the IEC-60958 standard and the S/PDIF standard,and then according to the actual engineering requirements and traditional shortcomings of the S/PDIF input interface,using the Verilog HDL hardware description language for RTL coding design,improve and optimize the S/PDIF interface.The design uses a digital circuit delay unit and a logic gate circuit to cleverly solve the problem of longdistance transmission data corruption issues.The synchronization module adopts the design of the improved two-stage synchronization mechanism,which flexibly avoids the problem of low synchronization fault tolerance caused by its traditional interface single-ended synchronization mechanism.Based on the two-level synchronization mechanism and the characteristics of BMC coding,this thesis proposes a design method of S/PDIF data valid flags combined with digital logical XOR gate decoding.This decoding method has high accuracy,weak clock correlation,and can effectively solve the disadvantages of the large integrated circuit area caused by the decoding scheme based on pattern recognition.This thesis chooses the simulation verification strategy driven by coverage.The simulation verification experiments based on the VCS tool confirmed that the S/PDIF input interface functions correctly,and the optimized design solves the above problems.The verification code coverage reaches more than 97% and the function coverage reaches 100%.In the comprehensive design phase,this thesis uses DC tools to comprehensively design the interface design timing,area,and power consumption.The comprehensive report shows that the interface circuit obtained by using the design method described in this thesis can reduce the area of the interface circuit by 10% compared with the previous generation interface circuit under the premise that the sequential power consumption meets the established requirements and the PVT parameters are unchanged.The work done in this thesis is the great significance for the development of related engineering fields.