UVM-based Verification Methodology For SATA AHCI

Serial Advanced Technology Attachment(SATA)is the most widely used high-capacity data interface in the industry.With the increase of the protocol and the performance,the verification requirements of SATA Advanced Host Controller Interface(AHCI)is also improved quickly.Universal Verification Methodology(UVM)developed on the basis of the SystemVerilog language is the latest generation of verification methodology,which greatly improved the completeness and efficiency of verification.However,the current verification testbench of SATA AHCI is based on traditional verification methodology.Therefore,it is extremely valuable in engineering for SATA AHCI to use UVM-based verification testbench.This paper adopts UVM to replace the original traditional verification methodology and completes SATA AHCI verification.UVM improves the completeness and efficiency of verification.There are a large number of test cases written in C language and used in past SATA AHCI verification.However,the test cases of the UVM verification platform are written in the SystemVerilog language.So,there is a problem that a large number of functionally similar code can no longer be used.This paper focuses on how to avoid drop these C test cases.The interface function between C and SystemVerilog is designed after this paper studied mixed compilation and UVM which can reuse most C test cases.Moreover,a randomization policy class is designed in order to raise the reusability of constraints.When all transaction classes extend from same base class,this policy class can manage and reuse constraints of these transaction objects because of hierarchical referring feature from UVM.It is not only efficiency is improved but also some constraint conflicts are avoided.Coverage and efficiency of SATA AHCI verification can be improved significantly with the UVM.In the end,the function coverage reaches 100%and the code coverage reaches 96.17%.After using the method of reuse C test cases described in this paper,40 C test cases(15,000 lines of code)are reused,accounting for 93.02%of existing C test cases.After using the random constraint policy class described in this paper,amount of code can be reduced by 99.69%of the Inline method and 36.44%of the Constraint method.