Research Of STA Optimization With A CPU Of ARM Framework On 7nm Process

With the evolution of integrated circuit industry,the manufacture of integrated circuit is advancing from 28 nm to 7nm、5nm even 3nm which follows the Moore’s Law.The promotion of integration level makes timing signoff in physical design for complex chip design harder and harder.How to get a more accurate timing analysis result which is identical with physical laws is one of the main tasks of chips’ physical design.This flow need to be precise enough as well as time-saving and resource-saving.Based on the module of a CPU design with ARM Cortex-A55 framework which contains about 930000 standard cells,the highest working frequency is about 2.198 Ghz.The physical design of this module is completed by Innovus,one P&R tool of Cadence.The timing analysis results are calculated by Innovus and timing signoff tool Tempus of Cadence.(1)With the netlist generated and mapped in i Spatial flow,the physical design of this module and timing analysis is completed with TSMC 7nm process.(2)The timing analysis results of this module is calculated in Path Based Analysis(PBA)mode in Statistic On Chip Variation(SOCV)method.The emulation results show that the STA results in PBA mode are better than those in Graph Based Analysis(GBA)mode.The worst negative slack(WNS)in PBA is-0.963 ns,better than that in GBA of-1.058 ns.The total negative slack(TNS)of the worst 10 paths in PBA is-9.583 ns,better than that in GBA of-10.506 ns.The timing analysis results meet the timing requirements of this design.(3)Based on the existing physical design flow,this research modifies the timing analysis method in different flow steps,then fixes the DRVs and optimizes the timing results.This modification improves the slack on the critical path.In pre CTS step in PBA mode,the WNS inproves from-0.041 ns to-0.033 ns for 19.51%.The TNS improves from-34.852 ns to-9.1132 ns for 73.85%.In post CTS step in PBA mode,the WNS improves from-0.063 ns to-0.047 ns for 25.40% and TNS improves from-97.308 ns to-85.631 ns for 12.00%.In post Route step,the WNS improves from-0.049 ns to-0.045 ns for 8.16% and the TNS improves from-56.973 ns to-53.163 ns for 6.69%.After ECO for the real timing violations in post Route step with the PBA results,the final WNS is-0.004 ns which meets the timing requirement of this module.In this flow,the workload of manual fixing is reduced.The thesis research,which analyses the timing results in PBA method of this module of the CPU design and raises an outlook for the disadvantage of PBA,has a certain engineering reference value to accurate STA analysis and optimization in digital IC implementation.