The Design And UVM Verification Of HyperRAM Controller

With the rapid development of Internet of things(IOT)technology,a variety of IOT devices emerge in an endless stream.Internet of things technology has produced many landmark applications in the fields of industry 4.0,smart city,smart home,connected automobile and electronic health.From the perspective of application scenarios,how to obtain IOT devices with lower power consumption and smaller area under the premise of ensuring performance is the primary consideration of major IOT manufacturers.Hyper RAM,which supports hyperbus protocol,is the latest solution to this requirement.Hyper RAM has become the preferred storage peripheral for Io T devices due to its advantages such as fewer interface pins,low power consumption and high performance.In order to control the logic function of Hyper RAM,a Hyper RAM controller is designed in this thesis.The information from AHB(Advanced High-performance Bus)bus is converted into hyperbus interface information and transmitted to Hyper RAM,so as to realize the read-write control and function configuration of Hyper RAM.This thesis presents the overall design structure of Hyper RAM controller,in which two AHB bus interface modules are used to receive bus information from MCU(Micro Controller Unit),one is used to transmit read-write data,the other is used to transmit register configuration values,and the register configuration module is used to configure and update controller registers and Hyper RAM internal function registers,The arbitration module is used to respond to data bus or register bus,and the delay control module is used to process center sampling and multi bit data calibration.In this thesis,the verification idea is proposed for the designed controller,the verification scheme is formulated,the UVM(Universal Verification Methodology)verification platform is built for functional simulation,and the test incentive is written for each verification function point to complete the simulation verification of the controller.After several iterations,the coverage analysis report that meets the expected results is finally obtained,in which the functional coverage is 100%,and the code coverage is 98.6%,All the printed logs show that the design is correct.In this thesis,the verification idea is proposed for the designed controller,the verification scheme is formulated,the UVM verification platform is built for functional simulation,and the test incentive is written for each verification function point to complete the simulation verification of the controller.After several iterations,the coverage analysis report that meets the expected results is finally obtained,in which the functional coverage is 100%,and the code coverage is 98.6%,All the printed logs show that the design is correct.