Design Of Large Capacity Storage Module For Broadband Oscilloscope

With the continuous development of electronic technology,acquisition technology and communication transmission technology,signal bandwidth and data volume become larger and larger.In order to improve the ability to capture these signals,it is necessary to develop digital oscilloscopes with higher sampling rate,larger storage depth and faster trigger rate.Therefore,based on the architecture of "host computer + multi-chip FPGA",this thesis completes the core device selection and overall scheme design of the wideband oscilloscope acquisition system,and designs and implements a large-capacity storage module with the maximum storage depth of 4Gpts on the acquisition system platform.In addition,the traditional oscilloscope has shortcomings in trigger accuracy and trigger rate,this thesis optimizes and designs each coprocessing module of the storage module,which improves the performance indicators of the storage module.The main research contents of this thesis are as follows:(1)By comparing and analyzing various memory devices,the scheme of using external DDR3-SDRAM memory chips to construct large-capacity data memory is determined,and the maximum storage depth of 4Gpts data memory is realized;At the same time,the status control module and address creating module are designed around the Memory Interface Generator(MIG)core of the storage controller,then the basic storage control module is encapsulated.(2)Based on the data characteristics of the acquisition system platform and the basic storage control module,the outer data processing module is designed.It not only improves the generality of the storage module,but also ensures the normal data interaction between the module and other functional modules on the acquisition system platform.Finally,based on the principle of "back pressure FIFO",the anti-overflow mechanism is designed in the path of data to ensure the security and integrity of data transmission.(3)This thesis studies the working principle of the original "two-stage trigger" module.In view of the disadvantages of large resource consumption,false trigger when collecting high frequency signal and trigger failure when collecting low frequency signal,the method of "first bit width conversion,then trigger point finding,and finally calculation compensation positioning" is proposed.In this way,the accurate location of trigger point is realized and the disadvantages of the traditional trigger module are solved.And the trigger precision of mass storage module is improved.(4)Based on the working principle of segmented storage,the design of the segmented storage control state machine is completed,and the basic storage control module and trigger module are optimized and improved in a targeted manner,so that the hardware module can independently trigger and store the collected waveform data for multiple times.It improves the trigger rate and storage space utilization of the largecapacity storage module in a short time.In addition,this thesis also analyzes the factors that affect the trigger rate.On the one hand,the response delay of the trigger module is reduced,on the other hand,the dead time of data acquisition between segments is shortened,which increases the trigger rate by more than 10 times and realizes the highspeed trigger mode.Through the test,verification and analysis of the above functional modules,the mass storage module designed in this thesis not only successfully achieves the maximum storage depth of 4Gpts under the single channel mode with the sampling rate of 20 GSPS,but also can accurately locate the position of trigger data points in the data memory.At the same time,it can achieve a high-speed trigger rate of 2,000,000 times per second at1ns/div time base and 100 pts storage depth.