Design And Simulation Of High-performance LDO

With the rapid development of semiconductor and communication technology,power management technology has been widely applied in various scenarios of the Internet of Things,and more and more technical personnel are interested in the research of power management chips.This thesis investigates the power management technology and market demand,and finds that low-dropout linear regulators(LDOs)are extensively used because of their advantages such as small area,simple structure,high stability,high power supply rejection ratio(PSR)and high efficiency.Aiming at the demand of portable management devices in Io T systems,the research direction of chips has shifted from large load current and high efficiency to high chip integration,low power consumption,high performance indicators and so on.Based on this background,this thesis designs a highperformance chip with low power consumption,high and high transient characteristics.The main work contents of this thesis are as follows:1、Based on the analysis of the influence of low static current on the performance of traditional LDO devices,this thesis optimizes the design of the modules for low power consumption.This thesis first analyzes the performance challenges brought by low static current to the device working state,speed and stability,then proposes the low power consumption design ideas for modules based on the analysis results,and introduces buffer stage and dynamic zero point compensation circuit for frequency compensation,which effectively solves the problem of insufficient stability of low power consumption negative feedback loop.2、This thesis analyzes the transient performance and power supply rejection ratio of low power consumption LDO and proposes optimization schemes based on this.This thesis adopts feedforward capacitor technique,adaptive bias current technique and an optimized transient enhancement circuit to improve the transient response of low power consumption LDO.Guided by theoretical calculations and analysis of power supply ripple feedthrough,the overall power supply rejection ratio of low power consumption is improved by enhancing the power ripple suppression ability of the voltage reference and optimizing the bandwidth and gain of the negative feedback loop circuit.3、By using the Cadence Virtuoso simulation platform,an LDO with low power consumption,high transient performance and high PSR is achieved based on Dongbu Hi Tek’s 0.18μm CMOS process.The LDO output voltage is 1.2 V and the maximum load current is 200 m A.The simulation results show that the overall quiescent current is1.262 μA;the load regulation is 6.1 μV/m A;the power supply regulation is 0.00964 %/V;when the load current jumps from 1 m A to 200 m A in 10 ns,the undershoot voltage is138.57 m V;when the load current drops from 200 m A to 1 m A in 10 ns,the output overshoot voltage is 75.27 m V.The low-frequency PSR is-90.398 dB and the 1 kHz PSR is-65.863 dB.