Circuit Design Of A Non-capacitive LDO Linear Regulator Based On 0.18?m CMOS Process

The non-capacitive LDO eliminates the parasitic bonding inductance and resistance of the traditional LDO due to the external passive components.After the integration of the LDO into a sealed module,power lines between the inductance,electromagnetic interference greatly reduced,while the reduction in the number of external components can bring lower noise and higher reliability,in the SOC system Widely used.Using a 0.18?m CMOS process,a non-capacitive LDO regulator circuit was designed using Cadence software,which including bandgap reference voltage circuit,error amplifier circuit,transient enhancement and frequency compensation circuit,adjustment tube and feedback resistor.The bandgap reference circuit uses a wide swing cascode cascade current mirror instead of an op amp,which the number of tubes reduces by 1/2 compared to the classical bandgap reference circuit with amplifiers,reducing the quiescent current and area of the overall circuit.Transient enhancement circuit using dynamic class AB transient enhancement circuit based on differentiator,to solve transient characteristics of the system.Frequency compensation circuit using Miller capacitor and dynamic class AB transient enhancement circuit based on differentiator is repeated as frequency compensation circuit,to solve the stability of the system.The simulation results show that when the input voltage is 2.1V,the output voltage is 1.8V,the voltage drop is 300mV,and the maximum load current is 100mA.The undershoot voltage is 60.07mV,the recovery time is 1.569?s,the overshoot voltage is 76.88mV,the recovery time is 2.119?s.At low frequencies,PSRR is-62dB.The quiescent current is 36.88?A.The overall layout area is 0.128mm~2.