Design And Implementation Of CAN Bus Controller Verification Platform Based On UVM

With the continuous improvement of semiconductor preparation technology,the scale of integrated circuit design continues to increase the complexity of circuits,so that chip verification is more and more important.The traditional verification method has some shortcomings,such as low efficiency,poor code reuse and non-repeatable process,so it can not be used for chip verification with high complexity.In order to solve these problems,Universal Verification Methodology(UVM)has been developed.It provides a set of standardized verification methods and a series of base libraries,which has the advantages of high verification efficiency,strong code reuse and high verification quality.It can effectively shorten the time spent by the verification personnel when building the verification platform,so as to reduce the related errors.In recent years,the development of automobile electronic Control technology makes the Control Area Network(CAN)bus technology develop rapidly.CAN bus controller is an important part of CAN bus technology,so its design and verification gradually become an important research direction.In this thesis,the CAN bus controller module in the laboratory research project is taken as the test design in the process of experiment,and a UVM verification platform is designed according to its working characteristics and the verification work is completed.The main research contents of this thesis are as follows:First,the UVM verification methodology and the basic knowledge of CAN bus are studied,and the communication mode and working characteristics of CAN bus controller module are analyzed.Focus on the analysis of its internal sub-module,register configuration and communication control mode.Functional verification points are extracted according to its two working modes and other functional features.The main extracted verification points include basic data sending and receiving function verification,stop sending function verification,self-receiving function verification,acceptance filter mode function verification,etc.Then,the architecture of UVM verification platform is designed according to the working mode and characteristics of CAN bus controller.The platform mainly designs and implements the following components: Can＿agent component which is used to configure the internal register of CAN controller;Can＿model＿agent component,which is used as virtual CAN bus node to communicate with DUT,can realize all functions in the process of DUT communication.The register models Ral＿block＿can and Ral＿block＿can＿peli correspond to two working modes of CAN controller Basic CAN and Peli CAN;Can＿scoreboard used to compare the correctness of the data sent and received by the controller in different modes;Can＿cgm components that automatically collect functional coverage during validation.The Transaction Level Modeling(TLM)communication mechanism is used to connect and communicate between components.In the verification process,random incentives are generated through sequence mechanism,and important mechanisms such as configuration mechanism,phase mechanism and factory mechanism are fully utilized to ensure the normal operation of the platform,improve the reusability of the verification platform,reduce the code complexity of each component,and make each component run independently and interconnect.Make the verification platform more organized.Finally,multiple test cases were written according to the extracted functional verification points.In the Linux environment,VCS simulation software and Makefile scripting language were used to run the simulation on the verification platform,and the test cases passed according to the log file and simulation waveform.The collection of coverage was completed by simulation software and Can＿cgm component.The overall code coverage reached 94.75% and the function coverage reached 100%,both meeting the expected goals and completing the verification of CAN bus controller module.Meet the design requirements.