Modules Design And Verification Technology Research Of DDR2 SDRAM Controller

Memory as an indispensable part of IC products, to some extent, has become the token of the development level of IC technique. DDR2 SDRAM is, at present, one of the most widely used kind of the memory. DDR2 interface controller is the control engine of DDR2 SDRAM access, and has broad utilities on both general-purpose computers and complex embedded systems. In this paper dissertation designs a compatible high-performance DDR2 SDRAM controller IP was implemented which is fully compatible to international standard and has complete functional characters needed as a high performance memory interface product. It will not only have a good application prospect, but also, for its design complexity, the accomplishment of this implementation can accumulate experience for enriching the the ability of independent memory controller design.This dissertation is mainly focused on the design of some vital modules of the DDR2 controller IP, architecture design of the verification platform, design of the basic components of functional verification and the execution of the whole verification process for the DDR2 SDRAM controller, including:1.The architecture design and function partition of the DDR2 memory controller: components are made up of the transport layer and physical layer, which were described respectively.2.Page-hit base commend reorder program was adopted to optimize the system bus, which, to a great extent, improves the utilization rate of SDRAM BUS.3.By using of ECC program as an error checking and correcting mechanism of the data access, the correctness rate and reliability of data access for the DDR2 memory controller was improved.4.Three important modules were described and implemented based on Verilog HDL, including arbiter module, the command reorder module and the error check and correction module..5.The functional verification platform of the DDR2 SDRAM controller was developed. First the architecture of the verification platform was achieved. Then the basic verification task modules were implemented including many kinds of bus functional models. Then the simulation of the whole design was fulfilled based on these bus functional models.