Design Of 32-Bit RISC-V Processor Based On FPGA

For a long time,the integrated circuit industry has been the focus of the development of our country’s information technology field,and processor design is one of the important components of the integrated circuit industry.However,whether it is in the field of personal computers,servers,or microcontrollers,the instruction set architecture authorization involved in processor design is strictly restricted.As an open source and efficient instruction set architecture,RISC-V is expected to become a breakthrough in the localization of processors under the wave of localization of chips.The main work is summarized as follows:1.The thesis studies the RISC-V instruction set architecture,and designs a five-stage pipeline processor core compatible with the RV32 IM subset based on the architecture.In the process of designing the pipeline structure,the more complex pipeline conflicts caused by the five-level pipeline structure compared with the two-level and three-level pipeline structure are analyzed,and corresponding solutions are designed.For the instructions related to division in the RV32 M instruction set,a special multi-cycle divider is designed.The divider can support the instructions related to division in combination with the pipeline stall mechanism of the processor core.2.In order to realize the simulation test of the instruction set compatibility of the processor core,run high-level language programs,and FPGA board-level verification,a So C is built on the basis of the processor core.The bus part of the So C refers to the principle of the Wishbone bus,and on this basis,the bus structure in the So C is simplified.The bus is equipped with four peripherals: ROM,RAM,UART,and Timer.3.In terms of simulation and verification,the instruction compatibility of the processor core was first simulated and tested.Aiming at repeated simulations in the iterative design of the processor,a Python script was used for the automatic instruction compliance testing,which reduced the time cost of the simulation process.Secondly,the function simulation of the peripherals on the bus is carried out by running the C language program.After ensuring that the interactive function between the processor core and peripherals is normal,the So C is verified on the NEXYS A7 FPGA development platform.After synthesis,placement and routing by Vivado,the total power consumption of the So C at a clock frequency of 33 MHz is only 0.208 W.Finally,the correctness of the So C function is verified by running the C language program and observing the program running results,and the RT-Thread nano operating system can be also started on the So C.