Processor Core Design And SoC Implementation Based On RISC-V Instruction Set

From smart watches to supercomputers,you can see the existence of processors.Processors are typical representatives of chips,and their importance is self-evident.At present,the processors on the market are mainly based on X86 and arm architecture,which are not open source and have high patent licensing barriers.RISC-V is an instruction set architecture that is completely open source and allows anyone to use.Under the guidance of autonomous control of key chips,it is of great significance to study RISC-V instruction set and use it to design processors.First of all,this thesis studies the RISC-V instruction set architecture and analyzes its advantages compared with other instruction set architectures,such as completely free and open source,module division of instruction set according to function,neat and efficient instruction coding,no branch delay slot and so on.This thesis also analyzes the six instruction formats of R-type,I-type,S-type,SB-type,U-type and UJ-type of the basic integer instruction set RV32 I.Secondly,this thesis designs a five stage pipeline processor core step by step.It designs the specific data path according to the functional characteristics of various instructions.It inserts the design of five stage pipeline and analyzes the advantages of doing so.It also analyzes the conflict problems in the pipeline and gives targeted solutions.The technology of bypassing the data in the execution and memory access stage to the decoding stage is used to solve the problem of data conflict.Instead of using the branch delay slot,the static branch prediction technology is used to solve the problem of control conflict.The processor core modules are divided and each module is specifically designed.The designed processor core is verified by writing a test program and using Modelsim simulation.The implementation of its five stage pipeline and the solution of conflict problems are verified,and the functional instructions such as integer operation instruction,memory access instruction and branch jump instruction are verified.Finally,on the basis of designing RISC-V processor core,this thesis uses AHB bus and APB bus as system bus,and modifies the design of peripheral UART,I2 C,GPIO and so on by using open source IP.Therefore,System on Chip(SoC)is built.The SoC is implemented and verified at board level by using Intel’s Cyclone IV E series FPGA.The results show that both the processor core and SoC can operate normally.