Research And Design Of Microprocessorrelated Modules Based On RISC-V Instruction Set Architecture

Chips are the core of the entire electronic information industry.With the advent of the era of "Internet of Everything",it will bring huge market space to smart devices and embedded devices.At the same time,as one of the largest consumer markets in the world,China has a very large demand for chips,but the strength of related domestic industries is subject to various constraints,resulting in a relatively weak development of the chip industry.At present,the mainstream instruction set architecture(such as ARM and x86)has been monopolized by foreign companies,and the instruction set architecture is the soul of processor design.In this case,the emergence of the RISC-V instruction set architecture has brought great opportunities to the development of the chip industry.Especially in the embedded field,RISC-V has the characteristics of free,concise,open source and low development difficulty,making it a pivotal position in the embedded chip market.At the same time,the RISC-V architecture has also opened a new path for the research and development and design of microprocessors in the era of artificial intelligence and embedded Internet of Things.The microprocessor designed in this paper is based on the fifth-generation RISC-V architecture.It not only supports the RV32 I instruction set,but also supports the extended instruction set of integer multiplication and division,including basic jump instructions,transfer instructions and operation instructions.The processor adopts a 3-stage pipeline structure.To improve the accuracy of branch prediction,the branch delay slot technology commonly used in RISC architecture processors is abandoned,and a static branch prediction mechanism is adopted,which greatly simplifies the hardware and further reduces power consumption and Improve timing.The low-speed module and the high-speed module bus interface are set inside the processor and are connected to the system bus for data access and transmission,so that each module in the entire system can achieve interconnection and function expansion.In this paper,after completing the complete architecture design of the system,a corresponding test platform is built to test and verify the performance and function of the processor.First,verify the functional correctness of the CPU(Central Processing Unit)core,including running the C language program test and the RISC-V basic instruction test.After the verification is passed,according to the characteristics of the peripheral units,a test program is written,and the functional integrity of each peripheral unit is tested accordingly.And run the Core Mark Benchmark program at a working frequency of 50 MHz and achieved a score of 2.86 Core Mark/MHz.All the verification results show that the processor functions normally and has good performance.After completing all the system verification work of the processor,the design of the processor is based on the TSMC 6 nm process for logic synthesis.In the logic synthesis stage,the system power consumption is reduced by adopting multi-threshold voltage technology,multi-bit registers technology and gated clock technology,and the performance parameters such as area and power consumption obtained after synthesis are optimized and studied.Finally,by analyzing and comparing various parameters,the processor is suitable for the embedded field and meets the design goals.