Secure SoC Design Based On RISC-V Instruction Set Architectur

With the development of IoT technology,SoC systems are becoming more and more widely used.However,highly integrated SoC systems often face security issues and these can have a negative impact on system performance and reliability.To address this issue,researchers have started to explore new embedded system design solutions.the RISC-V architecture has been gaining increasing interest in recent years due to its streamlined,flexible and open source features.At the same time,embedded systems need to communicate and interact with various peripherals,and also need to implement functions such as data encryption and decryption,so designing a secure SoC based on RISC-V architecture has become one of the hot topics of research.This paper presents a secure SoC design solution based on the RISCV instruction set architecture,which consists of the following aspects.Firstly,a RISC-V core IRISC suitable for embedded systems is selected and its instruction set is verified by hand coding.In order to realise the communication between the various components in the SoC system,key components such as the Wishbone-AHB bus bridge,AHB-APB bus bridge,UART module and AES algorithm module are designed in this paper.The AES algorithm module can effectively protect sensitive data in the system and further improve the security of the system by encrypting and decrypting it through secure communication protocols.the WishboneAHB bus bridge connects the Wishbone bus to the AHB bus,enabling the AES algorithm module to be mounted on the AHB bus,thus providing higher performance and efficiency.To verify that the communication between the SoC system and the external controller functions correctly,this paper designs the UART module and connects it to the CPU via the AHBAPB bus bridge.In addition,simulation verification and FPGA verification of each module are carried out in this paper.The results show that the designed modules work properly and reliably,and the security performance of the system has been significantly improved,which can effectively prevent common security attacks and meet practical application requirements,and can provide useful reference for future chip design.In summary,the secure SoC design based on RISC-V instruction set architecture proposed in this paper can effectively solve the security vulnerability and transmission efficiency problems in SoC systems.The innovation of this paper is to provide a secure SoC design scheme based on RISC-V instruction set architecture,which provides a new idea and method for the security of IoT devices,and has certain theoretical and practical significance for promoting the application and development of RISC-V architecture and improving chip security and reliability.The solution also has certain promotion and application value,and can be used in embedded systems,IoT devices and other fields.Future research will continue to explore the security and reliability of SoC systems in order to provide more comprehensive and efficient security solutions.