| A traffic recorder tester system is designed, implemented and tested on various Automated Traffic Recorders (ATRs). This dissertation discusses the algorithm developed to generate test vehicles, the modular design technique employed in design and implementation of the Test Vehicle Generator (TVG), and the design and implementation of the control software. The control software comprises user interface, device driver, performance analyzer, and communication software module. The TVG is connected to the parallel port of an IBM or compatible personal computer and is controlled by the device driver to output series of sensor activations in time domain. This time co-related test vehicle signatures simulate the passage of unambiguous Federal Highway Administration (FHWA) Type F vehicles over the sensor detection zone. The traffic data recorded by the ATR is then retrieved and compared with the traffic data generated by the system, and a performance report on the ATR is generated. The data retrieval from the ATR to the PC is through the serial communication port of the PC using an interrupt-driven communication software, and the performance report on the tested ATR is automatically generated by the performance analyzer module. In generating test vehicles, the accuracy of the time period between sensor activations is dependent on both the PC used to run the program and the compactness in coding the program. The techniques used to achieve the maximum timing accuracy are examined. The overall system performance is discussed. |
