The Research On Hardening Approaches To Single Event Effect In Nanoscale Digital Circuit

Single event effect is the main reason for spacecraft anomalies. In digital circuit, it mainly includes single event upset (SEU) which upsets the logic state of sequential element, and single event transient (SET) which acts as transient pulse in combinational logic and clock circuit. They can form a soft error, and influence circuit’s reliability. With technology scaling into nanometer, the device size and the supply voltage is falling, and SEU/SET becomes more serious. The clock frequency is rising, and SET from combinational logic is easier to form a soft error. Therefore, how to design integrated circuit which tolerates SEU/SET becomes an urgent problem to be solved.This dissertation researches on hardening approaches to SEU/SET, aimed at improving circuit’s reliability. At present, the existing hardening designs mainly mitigate SEU and (or) SET from combinational logic, and cannot mitigate SET form clock circuit. They suffer large overhead which influences circuit’s performance and cost, and affects practical application. For SET tolerance, a filter circuit is used at the end of combinational logic, such as time redundancy circuit, Schmitt trigger and CVSL gate. SEU tolerance methods include hardware redundancy, splitting internal node, error detection and correction, and cutting off feedback loop. For SEU/SET tolerance, time redundancy and hardware redundancy are used in combination, such as TR-TMR and TR-HLR, and the latch containing a delay element is used, such as FERST and LSEH-1.A single event hardening latch is proposed based on SMIC 65nm CMOS technology. It employs delay element and cascaded C-elements to constitute time redundancy which masks SET propagated from combinational logic. It also tolerates SET on clock signal because a delay element is embedded in the latch. Single particle striking induced logic upset of inner node brings C-element into hold state, which avoids impact on whole latch, and tolerates SEU. The simulation results show that it has no sensitive node to common mode fault, and tolerates SET on clock circuit, compared to the referred hardening designs. It also achieves 30.58% reduction in layout area,44.53% reduction in power, and 26.51% reduction in power of clock circuit, all on average. Moreover, its power is insensitive to process, supply voltage and temperature variations.