| According to attributes of PLC, this dissertation researches design of the PLC (Power Line Communication) system in the DSSS theory. The PLC system is discussed in detail and the implementation of PLC by the high-level design method, which is based on IP technology and analyses DSSS Specification comprehensively, is in the FPGA.The most advanced ASIC design technique is used in this research and it is described by VHDL, which belongs to hard ware description language. And the specific PCB was designed to verify the system on the FPGA.Finally, by means of the collector. This paper discusses the database software of the supervisor computer and implementation of database is by the Visual basic and Sql sever. This paper is clued by the design and implementation of IP core, and it expatiates on the subject of PLC chip and its system, which involves all processes of design, simulation and test. This paper introduces the design method of high-level design. In this research, the design of decoding DSSS on PLC chip is mainly discussed. Its premise is Specification of PLC ASIC chip communicating protocol and its sticking point is to analysis the function and architecture of PLC. All sub modules of PLC and its chip, which includes Master device and Target device are also discussed in detail in this paper. This dissertation archieves the design of PLC system and its system, and it has also completed the time-sequence and the function simulation of this IP core as well as timing simulation after placing & routing. A PCB board is designed to verify this PLC chip and the result of test proves the validity of this system. By means of database software, the database can receive the data and manage it at last. Finally, this dissertation introduce several key issues in designing and implementing PLC ASIC chip and PLC such as modulating and demodulating of the DSSS. At the same time, the thesis has analyzed the PLC system in terms of function and parts, which is formed the system.
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