Research On Optimization Of Media Digtal Signal Processor IP Core Design

Integrated circuit technology is developed so fast as Moore's theory (the number of thetransistors on single chip will be doubled every 18 months). The number of the gates on a chip hasexceeded ten million, However, the time-to-market becomes shorter and shorter. A chip designfrom the design specification to taping out may be finished in 5 months, which imposed greatpressure on designer. In order to meet the requirments of media systems which change quickly, theDSP processor is more and more powerful, various peripherals are integrated on the chip, and thespeed reaches GHz level.A DSP processor—MediaDSP1601 is developed by the Department of Information Scienceand Electronic Engineering in Zhejiang University, which has been successful fabricated under thecondition of SMIC 0.18um, running from 0-162MHz under 1.8V core voltage. On the base ofMediaDSP1601, this paper optimized MediaDSP1600 (MD16 for short) IP core facing toembedded media systems, focusing on the problem of instruction decoder, RISC pipelineoptimization, low power design, and related design when IP core is applied to systems.According to the specification, this paper performs the optimization of the instructiondecoder. Compared to the original one, the 2-layer decoding structure speeds up the instructiondecoding and the classified decoding structure consumes less power by shutting off unrelatedsub-decoder. After the optimization, the instructions are verified. A instruction verification flow isproposed based on the original verification platform for MD16, including instruction classification,instruction generation, instruction execution, results feedback, and coverage feedback.MD16 is characterized by its RISC-like pipeline. This paper performs the research onperformance optimization of the pipeline. Optimization techniques such as pipeling, logic copyand so on are applied to optimize the critical path by analyzing this path with data flowinformation. In order to lower the power consumption, clock-gating tenique is applied in RTLlevel by analyzing the structure of the core.As a IP core facing to embedded media systems, research on the related design is still neededafter the instruction decoder and pipeline optimization. This paper focuses on two problems ofdesign for test (DFT) and peripherals. An embedded debugger based on JTAG is integrated byanalyzing the characteristic of embedded media systems and IP reuse. And a UART isincorporated by analyzing the bus architecture.