| With the rapid development of CMOS technology, the System-on-Chip (SoC) which was integrated with more and more functional blocks has increasingly become the mainstream in the industrial designs.In SoC designs, in order to prevent the power supply noise of different functional blocks from affecting the performance of each other, it is often desirable that separate local power supplies being used by individual blocks. Under this circumstance,the development of full on-chip,external-pin-free low-dropout linear regulators (LDOs) can be beneficial from several perspectives.Firstly, the integration level of the SoC will be further enhanced.Secondly, the bill of materials form the PCB level can be significantly reduced.In this dissertation,we first introduced the typical topologies of LDOs and the performance parameters that are used to characterize them.Also,the design considerations that are typical in LDO design are summarized,such as the loop frequency compensation,transient response,noise performance, etc.In order to provide some insight and reference to the frequency compensation topologies of full on-chip LDOs, the design of large-capacitive-load three-stage amplifiers is discussed.After an in-depth discussion of the current buffer structure widely adopted in frequency compensation structures,we proposed a high-performance three-stage amplifier with nest Miller active-capacitor frequency compensation,together with the numerous transistor-level implementations of this amplifier.Subsequently, the design challenges of the full on-chip LDOs are discussed in detail along with the proposed area-efficient LDO structure which is capable of zero-to-maximum load stability.Finally, the chip fabrication and experimental results of the aforementioned three-stage amplifiers and LDO circuit are provided.In addition,performance comparisons with latest publication in literature are also provided to demonstrate the effectiveness of the proposed circuits. |
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