Algorithm Optimization And VLSI Implementation Design For The JPEG2000 Image Compression

Since the semiconductor company Analog Devices unveiled its first chip based on JPEG2000,Philips and other semiconductor companies also carried out JPEG2000 chip upon research and development work.About JPEG2000 standard core algorithm-wavelet transform and bit plane coding,since the correlation of their own complexity of the algorithm and data,has been a key factor affecting system performance.The optimization of the two core algorithm and structure improvement,become the focus of research at home and abroad.Therefore,the optimization and design of wavelet transform and bit plane coding is an important and challenging research topic.In this paper,the design and implementation of the wavelet transform coding and bit-plane carried out in-depth study and VLSI design,the main work is as follows:First,in-depth study of the wavelet transform algorithm and intermediate data related issues,discussed the analysis of the structure,In order to can ensure that the algorithm of real-time problem,when the design uses a fast algorithm of wavelet transform,optimize the structure of the natural line at the same time.While optimizing natural pipeline structure to ensure the processing rate algorithm,using wavelet transform parallel ranks,which is the use of the data transmission line caching mechanism.This structure can effectively save storage space and improve processing speed;Second,EBC as the main processing module of JPEG2000 codec upon process,itself--complex judgment logic structure,the characteristics of data and access frequency more frequently determines the design complexity.A single sample data to choose then output coding processing channel,there will be a slow processing speed of data encoding.Proposed an efficient bit plane coding(EBC)structure,through before coding the premise on a column for encoding data to deal with the channel,in the sample code arrives can directly into the code all coding,also used in channel coding of the predicted control of code complete data output;Third,for the two module connection module,this paper proposes a pretreatment of transmission in the middle of the module,used to connect the two core modules,to further improve the processing speed.Test results show that the optimized structure improved in terms of the encoding speed and throughput of the system is also obtained substantial ascension.