The FPGA Implementation Of Digital Signal Processing Algorithms In Imaging Sonar System

The underwater target within hundred miles can be displayed in image by imging sonar with high-frequency sound wave, then detection, trace, identification and database-building can be accomplished with the information of image. At present, imaging sonar has been applied in variety of domains, becoming more and more important in underwater target detection.The processor of the real-time imaging sonar sestem with high resolution should be able to handle large numbers of realtime data with high speed and high precision. This Field Programming Gate Array(FPGA) with powerful parallel treatment is selected as core processor in this thesis to study some important part of the imaging sonar system.First of all, The algorithm of FIR(Finite Inpulse Response)Filter and complex down-transducer always used in the digital signal preprocessing of the imaging sonar sestem is being studied and implemented in FPGA. The parameter of the FIR filter such as the cut-off frequency can be flexibly set according to the broad-band or narrow-band signal, which is received by the system and can fluently pass the filter. In order to lower the requirement of the analog filter and enhance the performance of it, cliffy transition band can be attained by adding the ranks of the FIR fliter. The complex down-transducer changing the real signal to the complex signal can avoid the appearance of target illegibility due to the double frequency band of the real signal when using FFT to realize the beamforming.Secondly, Fast Fourier Transform(FFT) Algorithm often used to realize beam forming is studied, serial and parallel cascade connection structure of the algorithm are designed. Fix point and block point operation are separately applied to each structure. In addition, the speed, resource and logic complexity are compared in each structure, Meanwhile, some optimization and improvement is also applied considering the characteristic of the butterfly operation.Finally, The frame of the DDR2 SDRAM controller is designed to explore the DDR2 SDRAM chip with 1Gbit capacity. All of this is prepared for the storage of large amount of data.