Design Of MiniSoC System Based On OpenRISC120032-bit CPU And The Software-hardware Co-verification

In the whole wide integrated circuit industry, almost every SoC is internalintegrated or applied with a CPU core. Because of the complexity of CPU designtechnology and high security, commercial processor and IP core is expensive, at thesame time, there are few public information on the internal logic implementation areintroduced in detail, as if the accumulation of experience in CPU design, reduceresearch object design cost and technical threshold is not suitable for. If you choose toopen source CPU series, will have a more complete information, such as CPU atpresent there are many, such as OpenRISC and LEON, here we select OpenRISCOR1200as the object in our research.OR1200is an open source processor for the OpenCores processor organization,based on the GPL protocol, its performance can be used for embedded systems ingeneral. At the same time, the OpenCores organization and some open sourceenthusiasts to provide a relatively complete open source IP core, the development ofinformation for researchers[40].This paper first introduces the basics of computer architecture, discusses theimportance of computer architecture for embedded processor design and testing, mainlyfor hardware and software features of the division, to determine hardware and softwareinterface. Understanding embedded processor design should consider the cost, price andtrends, performance evaluation and benchmarking process. Help software designers towrite high quality program, designers can provide design architecture processorsoftware better ensure the normal and efficient operation.This paper introduces addresses and addressing mode, the OpenRISC instructionset and pipeline instruction format, content, a detailed study of the composition of theOR1200core, Cache, MMU, DEBUG processor core architecture, the design unitfunction of data exchange and processing mode, grasp the overall system designcapacity of typical processors work independently, software debugging etc..In this paper, the Wishbone bus protocol and interconnection types analyzed indetail. Wishbone bus specification is a system-on-chip interconnection IP core architecture, need to integrate IP core bus specification compliance agreement toprovide the same common logical interface, easy to implement large-scale integrationand reuse, easy to transplant, both validation and reliability resistance are improved[1].After analyzing the processor architecture, the design miniSoC system download tothe FPGA hardware platform, the software and hardware achieve the miniSoC systemverification based on Cygwin for software development environment and tools forporting and testing, this miniSoC system is integrated with easy to follow multi-IP, andcollaborative software developed.