Research And Design Of A High-PSR Low Dropout Regulator

Power management circuit is an essential module for all electronic products.Voltage regulation is a basic and widely used function of the Power managementcircuit. The most commonly used circuit in the field of voltage regulation is lowdropout regulator (LDO). It is widely presented in the communication electronics,automotive electronics and SOC. Especially for power supply noise sensitive analogand RF circuits, LDO is preferred as power supply circuit generally.With the development of CMOS technology， the channel size and thesupply-voltage are reduced. The decrease of supply-voltage increases the sensitivityof IC towards the power noise. So it is very important to study the method to increasePower-supply ripple rejection of LDO.Based on the analysis of technological developments of LDO PSR, this paperstudied and analyzed the Feed-Forward Ripple Cancellation technique. Finally theFFRC structure was adopted to design a high-PSR LDO. The pole splitting and ESRcompensation technique was adopted to achieve the stability of LDO. This paper alsostudied the method to improve the PSR of bandgap and a kind of high-PSR bandgapwas designed.Matlab simulink software was used to model and analyze the system and todetermine the parameters of the circuit modules. And the Cadence software was usedto design and simulate all the circuit modules. The circuit was implemented in UMC0.18μm CMOS technology. The output voltage of LDO is1.8V. The operatingvoltage range is2V to5V.The Load current range is0to30mA. Dropout Voltage isless than200mA. Quiescent Current is less than100μA.The maximum LinearRegulation is0.0021%/v. The maximum Load Regulation is23μV/mA. When theinput voltage is2V, the PSR|DCis80dB and PSR|1Mhzis60dB. On the load-currentstep signal from0to30mA, the overshoot voltage is less than10mV. The simulationresults revealed that this design meets the design target.