Design And Study Of Two-Phase Interleaved, Large-Current, Synchronous Boost DC-DC Converter

With the rapid development of portable electronic products and large scale integrated circuit, the traditional power supply with single DC-DC converter cannot meet the more critical application requirement, such as, heavier load, higher efficiency, smaller ripple, higher frequency, and smaller volume. But multiphase interleaved technology which is based on phase-locked loop clock synchronization function can implement multiple DC-DC converters supply power in parallel to overcome the shortcoming of single converter.In this paper, based on synchronous boost DC-DC converter, combined with multiphase interleaved technology and charge-pump phase-locked loop technology, a tow-phase interleaved synchronous boost DC-DC converter is designed to meet the application of different frequency, heavy load and small output voltage ripple. On the basis of analyzing the operating principle of synchronous boost DC-DC converter, peak current mode control is adopted to decrease the difficulty of loop compensation and improve the transient response speed to supply voltage and load variety; PWM/PSM mixed modulation mode can improve the converter's efficiency under full load range, by applying PWM modulation when at heavy load, and applying PSM modulation when at light load; Applying pre-charge and inductor current step-up method to eliminate the inrush-current and over-shoot voltage. The small signal model and stability of synchronous boost DC-DC converter applied with peak current mode have been analyzed, and the second order compensation for this converter is calculated in detail to determine the compensation parameters. Besides introducing the principle of current share and two-phase interleaved, the operation condition which is under continuous conduction mode of two-phase interleaved has been emphasized on, and double-master tow-phase interleaved is implemented to share load current to meet the application of heavier load, higher efficiency, smaller ripple, and higher frequency. On the basis of analyzing the operation principle of charge-pump phase-locked loop and problems should be paid attention to in circuit designing, practical circuit of sub-module of charge-pump phase-locked loop which can synchronous 300~1000k Hz external clock has been implemented meet different frequency application. The key sub-module, such as, reference circuit, error amplifier, is also analyzed and designed in detail. Besides, the chip is also integrated over temperature protection, input under-voltage lock, input over-current protection, output over-voltage protection, and output short protection circuits to improve the reliability of the chip.The two-phase interleaved, large current synchronous boost DC-DC chip presented in this paper is based on 0.35?m standard CMOS process. Based on Cadence software platform, using Spectre simulator, the performance of the key sub-model of this chip, the function of single chip application, and the function of two-phase interleaved with large current have been verified. The superiority of two-phase interleaved is presented to suppress the ripple of output voltage by comparing the simulation results of single chip with two-phase interleaved chip.