Design Of A Charge-pump PLL For Buck DC-DC Converter

With the rapid development of integrated circuit and semiconductor technology, power management ICs have been widely used in the areas of communication network, computer and electronics. Among all the power management chip, switching power supply is the most widely used because of its high reliability, high efficiency, high frequency and high power density. In addition, Buck DC-DC converters integrated with PLL has many advantages, such as high power conversion efficiency, fast load transient response, strong load capacity and so on. But the noise and phase jitter caused by the PLL have certain effect on the stability of the converters. So the study of high reliability PLL for Buck DC-DC converters is of great significance.The PLL designed in this paper is integrated in a Buck DC-DC converter, and it provides a high reliability clock signal for the converter. On the basic of discussing the structure and important characteristics of PLL, this paper derives its loop transfer function and analyzes its loop response. Charge-pump PLL is consisted of five parts, including phase and frequency detector, charge-pump, loop filter, voltage-controlled oscillator and frequency divider. In this paper, the structure of phase and frequency detector is based on the D flip-flop, and the ’dead-zone’ of it is reduced by prolonging the delay time of the reset circuit, while maintaining that it has a wide range of phase detection and rapid capture speed. Charge-pump adopts the source mode, which has a good performance in solving current mismatching and charge injection effect. And also, the symmetrical current mirror included in the charge-pump is beneficial to improve the matching of the circuit and reduce the sensitivity to the digital signal jumps, and it can reduce the jitter of the control voltage of the VCO yet. Taking the aspects of linearity, noise, frequency regulation range,integration difficulty, power consumption, and stability into account, the loop filter uses traditional 2-order passive filter, which is simple and efficient. Besides, the voltage controlled oscillator can be divided into two parts. The first part is V-I circuit, which uses the differential pair structure to ensure the small distortion and good noise suppression performance. The second part is the oscillation circuit, which generates oscillation signals through charging and discharging the capacitor. The oscillation circuit characterized by charging and discharging at the same time. It strengthens the continuity of the circuit,while the output waveform of the VCO is more stable and regular.The design is based on standard 0.35μm CMOS technology. The chip’s circuit design and simulation are completed in the Cadence software platform. The frequency range of this PLL is 250~750k Hz. Its locking time is less than 60μs and phase jitter is less than 20 ns.Beyond that, when the input power supply voltage is dropping to 2.4V, the circuit can work normally either.